Segmented Full Adder Logic for Glitch-Balanced Sum Output
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Solution Overview
Problem
Conventional full adders suffer from unbalance and glitches in their output signals due to relative delays and poor balance in logic cells, which affect signal synchronization and lead to detrimental cascading effects.
Innovation Solution
The implementation of a full adder using a plurality of primary logic cells and secondary logic cells, where output terminals of primary cells are connected to input terminals of secondary cells, allowing intermediate signals to be processed in sequential stages, reducing the need for logic operations within the same cell and minimizing glitches by ensuring synchronization and using balanced logic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional full adder logic cells perform multiple logic operations simultaneously, then computation speed is improved, but signal balance deteriorates and glitches increase
Solution Approach 1:
The full adder logic cell is segmented into multiple independent logic modules, each responsible for specific intermediate signal generation. This segmentation allows simultaneous computation in different modules while maintaining signal balance within each module, resolving the contradiction between computation speed and signal balance.
Solution Approach 2:
Intermediate signals are generated in advance by dedicated logic cells before the final sum and carry operations. This preliminary action prepares signals for subsequent operations without causing timing conflicts or balance deterioration in the main computation path.
2Device complexity
If logic operations are performed on input and intermediate signals within the same cell, then device complexity is reduced, but signal synchronization deteriorates and errors increase
Solution Approach 1:
The logic cell is divided into multiple independent units, each handling specific signal processing tasks. This segmentation prevents simultaneous operations on input and intermediate signals within the same logical unit, eliminating synchronization conflicts while maintaining manageable device complexity through modular design.
Solution Approach 2:
Intermediate signals serve as mediators between input signals and final outputs. Dedicated logic cells process these intermediate signals separately, ensuring proper synchronization without requiring complex coordination within a single logic cell.
3Productivity
If multiple logic operations are performed in parallel, then productivity is improved, but harmful factors increase due to glitches
Solution Approach 1:
Parallel logic operations are segmented into separate modular units, each performing specific functions. This segmentation enables productive parallel computation while isolating potential glitch sources to individual modules, preventing glitch propagation across the entire circuit.
Solution Approach 2:
The design accepts that parallel operations may generate local glitches but uses the modular segmented structure to contain and manage these glitches. The segmented architecture converts the potential harm of parallel operation glitches into manageable local issues that do not affect overall circuit reliability.
Data Source
AI summary
Full adder, a chip and a computing device are disclosed. A full adder includes: a plurality of primary logic cells and at least one secondary logic cell, wherein an output terminal of each primary logic cell is at least connected to an input terminal of a first secondary logic cell in the at least one secondary logic cell. The plurality of primary logic cells includes: a first primary logic cell, a second primary logic cell and a third primary logic cell respectively configured to generate a first intermediate signal, a second intermediate signal and a carry-related signal based on a first input signal, a second input signal and a carry input signal input to the full adder. Furthermore, the first secondary logic cell is configured to generate a sum output signal of the full adder based on the first intermediate signal, the second intermediate signal and the carry-related signal.