Full-Adder Reconfigurable Logic for FPGA Crypto Mapping
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Solution Overview
Problem
Current reconfigurable logic circuits for cryptography in FPGAs face limitations in terms of area requirements and throughput, and require more logical resources compared to commercial FPGA solutions, while also being inflexible in mapping regular HDL code.
Innovation Solution
A reconfigurable logic circuit with a full-adder-based cell structure that includes switching circuits and logic blocks for implementing arithmetic functions, allowing for efficient configuration of logical functions and protection against side-channel attacks, using a combination of AND and OR logic blocks and configuration bits to optimize area and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a reconfigurable logic circuit with full-adder-based cell structure is used, then area efficiency is improved, but the ability to map regular HDL code deteriorates
Solution Approach 1:
The reconfigurable logic circuit is designed with a universal cell structure that can implement multiple cryptographic functions (AES, Serpent, RC6, Rijndael) through configuration bits. The full-adder-based cell with switching circuits can be programmed to perform different logical operations, making it adaptable to various HDL code mappings while maintaining area efficiency.
Solution Approach 2:
The circuit uses configuration bits to change the operational parameters of the full-adder-based cell, allowing it to switch between different logical functions. This parameter-based reconfiguration enables the circuit to adapt to different HDL code requirements without changing the physical structure, thus maintaining both area efficiency and mapping flexibility.
2Productivity
If switching circuits and logic blocks are used to implement arithmetic functions, then throughput is improved, but the number of configuration bits increases
Solution Approach 1:
The design merges the functionality of multiple separate circuits into a unified full-adder-based cell structure. By combining arithmetic functions, logical operations, and reconfiguration capabilities into a single cell type, the number of different cell variants is reduced, which decreases the overall number of configuration bits required while maintaining high throughput through efficient arithmetic operations.
3Productivity
If dedicated circuits for cryptographic functions are used, then throughput is improved, but area requirements increase
Solution Approach 1:
The circuit employs dynamic reconfiguration capabilities where the same physical hardware can be programmed to perform different cryptographic functions. This dynamic adaptability allows dedicated circuits to be created on-demand for specific functions, achieving high throughput for each function while avoiding the permanent area overhead of having multiple dedicated circuits simultaneously.
Data Source
AI summary
A reconfigurable logic circuit comprises first, second and third switching circuits arranged for receiving first, second and third input bits, respectively, and each arranged for being configured in a mode wherein the corresponding input bit is passed on or in a mode; a first exclusive OR logic block operable on the outputs of the first, second and third switching circuits and arranged to output a sum bit; fourth, fifth and sixth switching circuits arranged for receiving a fourth, fifth and sixth input bits and arranged for being configured in a mode; first, second and third AND logic blocks, each arranged for receiving a different pair of the outputs of certain switching circuits; a second exclusive OR logic block operable on the outputs of certain AND logic blocks and arranged to produce a carry output bit.