Full Adder Cell Topology With Fewer Transistors and Lower Power
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Solution Overview
Problem
Conventional full adder circuits consume significant power and occupy large areas due to the high number of transistors required, which is a challenge in developing more powerful digital logic circuits in smaller form factors with faster timing responses.
Innovation Solution
The design incorporates a two-input NAND gate combined with an OR-AND-INVERTER (OAI) cell, utilizing an XNOR cell to generate a carry out signal, and a pass gate structure for the sum output, which reduces the number of transistors and shares signals between logic stages, resulting in a more efficient full adder circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional full adder circuits are implemented using multiple transistors arranged as inverters, pass gates, AND gates, OR gates, and XOR gates, then the circuit achieves complete full adder functionality, but the circuit occupies significant chip area and consumes high power due to the large number of transistors required
Solution Approach 1:
The patent combines multiple logic gates into integrated gate structures. Specifically, it uses OR-AND-INVERTER (OAI) cells that integrate OR and AND gate functionality with inversion, and NAND gate structures that combine multiple logic operations. This merging reduces the total number of discrete transistors needed while maintaining full adder functionality, directly addressing the chip area reduction goal
2Reliability
If conventional full adder circuits use multiple transistors for complete logic functionality, then the circuit achieves accurate sum and carry out generation, but the circuit consumes significant power
Solution Approach 1:
The patent merges multiple logic operations into single integrated gate structures like OAI cells and NAND gates. This consolidation reduces the number of transistor switches and interconnections, thereby reducing dynamic power consumption while maintaining the ability to generate correct sum and carry out signals through the integrated logic functionality
3Reliability
If conventional full adder circuits implement complete logic using multiple gates, then the circuit achieves correct addition operation, but the circuit exhibits larger timing delay
Solution Approach 1:
The patent integrates multiple logic operations into single gate structures, reducing the number of sequential logic stages. The OAI cells and NAND gate structures perform multiple logic operations in parallel within a single gate delay, thereby reducing the overall propagation delay while maintaining correct full adder operation through the integrated logic design
Data Source
AI summary
An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.