Full Adder With Separate Sum And Carry Logic Circuits
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Solution Overview
Problem
Conventional full adders consume substantial power and operate slowly due to shared internal circuit nodes with parasitic capacitance and contention between logic gates, which hampers their performance in digital cores.
Innovation Solution
A full adder design featuring separate sum and carry-out logic circuits, each driven by a single logic gate, eliminating the need for transmission gates and reducing parasitic capacitance, thereby minimizing power consumption and increasing operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional full adders use shared internal circuit nodes for carry-out and sum paths, then circuit density is improved, but power consumption increases and operating speed decreases due to parasitic capacitance
Solution Approach 1:
The full adder is divided into separate sum logic circuit and carry-out logic circuit with dedicated internal nodes. The sum path includes sum generate nodes and sum propagate nodes, while the carry-out path has its own dedicated nodes. This segmentation eliminates shared nodes and their associated parasitic capacitance, reducing power consumption while maintaining acceptable density through efficient layout of the separated circuits.
2Area of stationary object
If conventional full adders use shared internal circuit nodes for carry-out and sum paths, then circuit density is improved, but operating speed decreases due to parasitic capacitance
Solution Approach 1:
The full adder is divided into separate sum logic circuit and carry-out logic circuit with dedicated internal nodes. The sum path includes sum generate nodes and sum propagate nodes, while the carry-out path has its own dedicated nodes. This segmentation eliminates shared nodes and their associated parasitic capacitance, reducing power consumption while maintaining acceptable density through efficient layout of the separated circuits.
3Reliability
If conventional full adders use transmission gates to resolve contention between logic gates, then output node contention is managed, but power consumption increases and operating speed decreases due to transmission gate struggle
Solution Approach 1:
The invention extracts and eliminates the transmission gates from the conventional full adder design. Instead of using transmission gates to manage contention between logic gates driving the sum and carry-out nodes, the design uses dedicated logic gates for each path that naturally resolve contention without requiring transmission gates, thereby reducing power consumption and eliminating the transmission gate struggle effect.
4Reliability
If conventional full adders use transmission gates to resolve contention between logic gates, then output node contention is managed, but operating speed decreases due to transmission gate struggle
Solution Approach 1:
The invention extracts and eliminates the transmission gates from the conventional full adder design. Instead of using transmission gates to manage contention between logic gates driving the sum and carry-out nodes, the design uses dedicated logic gates for each path that naturally resolve contention without requiring transmission gates, thereby reducing power consumption and eliminating the transmission gate struggle effect.
Data Source
AI summary
A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.