Full Adder Circuit Transistor Reduction
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Solution Overview
Problem
Full adder circuits in digital signal processing systems are inefficient due to the large number of transistors required, leading to increased chip layout size and threshold pass delay, especially as the number of input signals increases.
Innovation Solution
A full adder circuit design utilizing three logical operation units that perform XOR and NAND operations using inverters and transmission gates to generate sum and carry output signals, reducing the number of transistors required by using inverse signals, resulting in a more compact and efficient circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional full adder circuit design using 3 NAND gates is used, then the circuit can generate sum and carry output signals, but the number of transistors increases to 12, leading to increased chip layout size and threshold pass delay
Solution Approach 1:
The patent merges the functionality of multiple gates into three logical operation units that each perform multiple functions. Each unit combines inversion, transmission, and logical operation capabilities, reducing the total transistor count from 12 to 8 while maintaining full adder functionality.
Solution Approach 2:
Each logical operation unit is designed to perform multiple functions: inverting signals, transmitting signals conditionally, and performing logical operations. This multi-functionality reduces the need for separate dedicated gates, thereby reducing the overall transistor count.
2Productivity
If the number of input signals for operation increases, then the data processing capability increases, but the number of transistors and chip layout size increase, causing performance degradation
Solution Approach 1:
The patent changes the operational parameters by using inverse signals and conditional transmission to reduce the transistor count. This allows the circuit to handle increased input signals with fewer transistors, maintaining performance while increasing capability.
3Productivity
If traditional full adder design with 12 transistors is used, then the circuit can process data, but the threshold pass delay increases, reducing data processing speed
Solution Approach 1:
The patent extracts and eliminates unnecessary transistors from the traditional 12-transistor design, retaining only the essential components needed for functionality. This reduction in transistor count directly decreases the threshold pass delay and improves data processing speed.
Data Source
AI summary
A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal.