Full-Bridge Control Circuit Logic XOR Noise Immunity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing control circuits for full-bridge power stages in PWM driving of electric loads suffer from spurious switching of logic driving signals, which are prone to corruption by switching noise, especially when controlling low resistance loads with small currents and significant back-electromotive forces.

Innovation Solution

A control circuit that generates PWM and logic driving signals within the feedback loop by logically combining signals PwmA and PwmB, using active switching edges to produce a logic driving signal that is immune to switching noise, and employs linear drivers for low current conditions to maintain effective control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the logic driving signal is generated by comparing the error amplifier output with a reference threshold, then the current direction can be controlled, but spurious switching occurs due to switching noise corruption

Engineering Contradiction:
Improvelogic driving signal stabilityVSAvoidswitching noise corruption
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary logic processing stage between the error amplifier output and the logic driving signal generation. Instead of directly comparing the error amplifier output with a reference threshold, the system processes the PWM signals through logic operations (XOR, AND, OR gates) to generate the logic driving signal. This intermediary logic processing filters out switching noise and prevents spurious switching while maintaining accurate current direction control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If PWM mode is used for driving the half-bridge, then high efficiency is achieved, but spurious switching of logic driving signals occurs due to noise

Engineering Contradiction:
Improvepower efficiencyVSAvoidlogic driving signal accuracy
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent maintains PWM mode for efficient power conversion while introducing logic processing as an intermediary layer. The PWM signals from the power stage are processed through logic gates (XOR to detect edges, AND/OR to combine signals) before generating the logic driving signal. This intermediary logic processing preserves the efficiency benefits of PWM while filtering out the switching noise that would otherwise cause spurious switching.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If the duty-cycle is adjusted to control current intensity, then the current magnitude can be regulated, but spurious switching occurs when controlling low resistance loads with small currents

Engineering Contradiction:
Improvecurrent intensity controlVSAvoidswitching noise impact
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent uses logic processing as an intermediary between the duty-cycle controlled PWM signals and the logic driving signal. The logic gates process the PWM signals to extract the essential control information while filtering out switching noise. This approach maintains precise current intensity control through duty-cycle adjustment while preventing noise-induced spurious switching, especially critical for low resistance loads with small currents.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8207695B2Control circuit of a full-bridge stage
Publication Date: 2012.06.26 STMICROELECTRONICS SRL
  • US8207695B2 patent drawing
  • US8207695B2 patent drawing
  • US8207695B2 patent drawing

AI summary

A control circuit for a full-bridge-stage to drive an electric load includes PWM generation circuitry for generating first and second PWM signals so that a difference between duty-cycles of the PWM signals represents an amplitude of a drive current. A logic XOR gate is input with the first and second PWM signals and generates a logic XOR signal. A logic sampling circuit generates a logic driving command of a half-bridge stage, a logic value of which corresponds to a sign of the drive current, by sampling one of the first and second PWM signals based upon active switching edges of the logic XOR signal. A second XOR gate generates a third PWM driving signal of the other half-bridge of the full-bridge stage, a duty-cycle of which corresponds to the amplitude of the drive current.