Full-Chip Cell CD Correction via Density Map Retargeting

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Solution Overview

Problem

Existing methods for manufacturing masks in semiconductor processes struggle to effectively correct cell critical dimension (CD) errors across a full-chip, leading to inaccuracies in pattern transfer and increased defects.

Innovation Solution

A method involving the generation of a density map for a full-chip, conversion into a retarget rule table, reconfiguration of cell blocks into an optical proximity correction (OPC) target cell layout, application of biases based on the retarget rule table, and performing hierarchical OPC to generate an optical proximity corrected (OPC'ed) layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing mask manufacturing methods are used, then the process is simple and fast, but cell critical dimension errors cannot be effectively corrected across the full-chip

Engineering Contradiction:
Improvecell critical dimension accuracyVSAvoidcorrection process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The full-chip layout is divided into multiple cell blocks, which are further segmented into individual cells. This hierarchical segmentation allows the correction process to be applied systematically across the entire chip while managing complexity through modular processing of smaller units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A density map is generated and analyzed before the actual OPC correction is applied. The retarget rule table is prepared in advance based on the density analysis, allowing the correction process to use pre-calculated parameters rather than computing everything during the correction phase.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If conventional OPC methods are applied, then the manufacturing process remains simple, but pattern transfer accuracy deteriorates due to uncorrected CD errors

Engineering Contradiction:
Improvepattern transfer accuracyVSAvoidcorrection processing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The density map generation and retarget rule table creation are performed as preliminary steps before the actual OPC correction. This allows the complex calculations to be done once in advance, making the subsequent correction process more efficient and reducing overall processing time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The correction process applies different biases to different cells based on their local density characteristics. Each cell receives a customized correction amount determined by its position in the density map, allowing precise local adjustments without requiring full-chip reprocessing.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If no density-based correction is applied, then the process is fast and simple, but CD errors vary significantly across different regions of the full-chip

Engineering Contradiction:
ImproveCD uniformity across full-chipVSAvoiddensity analysis and bias application
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies different correction biases to different regions of the chip based on the density map. High-density regions receive one type of correction while low-density regions receive another, ensuring uniform CD control across the entire chip by addressing local variations specifically.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The density map serves as an intermediary data structure that captures the spatial distribution of pattern density across the chip. This intermediate representation allows the system to analyze density variations and translate them into appropriate correction parameters without directly manipulating the original layout data.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12282249B2Full-chip cell critical dimension correction method and method of manufacturing mask using the same
Publication Date: 2025.04.22 SAMSUNG ELECTRONICS CO LTD
  • US12282249B2 patent drawing
  • US12282249B2 patent drawing
  • US12282249B2 patent drawing

AI summary

A full-chip cell critical dimension (CD) correction method and a method of manufacturing a mask by using the same are provided. The full-chip cell CD correction method includes receiving a database (DB) about a full-shot; analyzing a hierarchy of the DB; generating a density map of a full-chip by using the DB and converting the density map into a retarget rule table, the converting including mapping the density map by using a density rule; reconfiguring cell blocks of the full-chip into an optical proximity correction (OPC) target cell layout for OPC; applying a first bias to the OPC target cell layout, based on the retarget rule table; and generating an optical proximity corrected (OPC'ed) layout for the full-chip by performing hierarchical OPC.