Full-Chip Signal-Power Simulation for Jitter and Eye Diagram Analysis
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Solution Overview
Problem
Conventional methods for analyzing signal and power integrity in high-speed SoC systems lead to inefficient use of resources and increased area/power consumption due to separate analysis of input/output interfaces, packages, and printed circuit boards, failing to consider their integrated performance.
Innovation Solution
A simulation system and method that integrates signal and power integrity analysis by creating abstract models of a full chip system, using a simulation program to simulate current and voltage responses, jitter, and power noise, enabling comprehensive simulation of signal integrity and power integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional independent analysis methods are used for input/output interfaces, package, and printed circuit board, then each component can be analyzed separately, but it causes consumption of excessive manpower and material resources and wastage of area/power consumption
Solution Approach 1:
The patent merges signal integrity analysis and power integrity analysis into a single integrated simulation system. The system establishes a unified simulation model that includes both signal channels and power distribution networks, allowing simultaneous analysis of both integrity aspects. This integration eliminates the need for separate independent analyses, reducing computational resources, manpower, and power consumption while maintaining comprehensive analysis capability.
Solution Approach 2:
The simulation system is designed with multi-functionality to perform both signal integrity analysis and power integrity analysis through a single unified platform. The system can analyze multiple aspects (signal transmission, power distribution, noise coupling) simultaneously using the same simulation infrastructure, making the analysis process more efficient and reducing resource wastage.
2Speed
If high working speed and high data transmission rate are achieved in SoC, then system performance is improved, but signal integrity and power integrity become increasingly affected and interdependent
Solution Approach 1:
The patent addresses the increasing interdependence by merging signal integrity and power integrity analyses into a unified simulation framework. The system models the coupled effects between signal channels and power distribution networks, allowing the analysis of how power noise affects signal quality and how signal switching affects power integrity. This integrated approach manages the complexity arising from high-speed operation by treating the interdependent phenomena together rather than separately.
3Measurement precision
If quantitative analysis of independent performance requirements is performed for each component, then detailed component-level insights are obtained, but it leads to excessive resource consumption and inefficiency
Solution Approach 1:
The patent combines component-level detailed analysis with system-level efficiency by implementing an integrated simulation that maintains precise modeling of individual components (input/output interfaces, package, printed circuit board, SoC) while analyzing them within a unified system framework. This approach preserves measurement precision for each component while improving overall productivity by eliminating redundant separate analyses and enabling parallel computation of interdependent phenomena.
Data Source
AI summary
A simulation system and a method thereof are disclosed. In the simulation system, a system power transmission model, and analog current time-domain model and digital current time-domain model are connected to obtain power noise generated after a supply current is obtained; jitter time-domain information of each interface connection circuit model under the power noise is obtained based on transmission of a clock signal outputted from a phase lock loop, by a simulation program; next, a voltage step response of a voltage measurement point when a clock terminal of each interface connection circuit model receives an ideal signal, is simulated by the simulation program to generate a first voltage time-domain model; a system waveform is generated based on the jitter time-domain information of each interface connection circuit model under the power noise, the first voltage time-domain model and data transmission, thereby obtaining an eye diagram and time-domain jitter distribution.