Full-Chip Optimization With Reduced Physical Design Data
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Solution Overview
Problem
Current hierarchical electronic design methodologies face challenges in achieving full-chip optimization due to increased complexity and memory utilization in very deep sub-micron integrated circuits, particularly in reducing physical design data while ensuring design closure and timing optimization across block boundaries.
Innovation Solution
A method and system for full-chip optimization that allows concurrent optimization at both the top-level and block-level, using a reduced set of physical design data, which includes identifying original design data, performing hierarchical exploration, time budgeting, and assembling the design, while merging changes back into the original data set, and generating reduced physical design data for optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional hierarchical design methodology is used with black boxes or macro libraries to represent blocks, then design complexity is reduced and ease of operation is improved, but full-chip optimization cannot be achieved and manufacturing precision deteriorates
Solution Approach 1:
The patent segments the design data into two categories: complete netlist data for timing analysis and reduced physical design data for optimization. This segmentation allows the system to maintain ease of hierarchical design operation while achieving full-chip optimization by using the reduced data set specifically for optimization activities where precision is critical.
Solution Approach 2:
The patent introduces an intermediary reduced physical design data set that acts as a bridge between the complete netlist and the optimization process. This intermediary contains only the necessary physical design information (placement, routing, parasitics) needed for optimization, allowing full-chip optimization without requiring the complete netlist, thus resolving the contradiction between ease of operation and optimization precision.
2Productivity
If active logic reduction technology is used to reduce physical design data, then data size is reduced and processing speed is improved, but optimization is limited to timing graph reduction and cannot modify the entire electronic design
Solution Approach 1:
The patent applies partial action by including only the necessary physical design data (placement, routing, parasitics) in the reduced data set, excluding unnecessary logic details. This partial inclusion enables both fast processing and comprehensive design modification capability, as the reduced data is sufficient for full-chip optimization while maintaining productivity.
Solution Approach 2:
The patent changes the parameters of the physical design data by transforming the complete netlist into a reduced data set that retains critical physical parameters (placement coordinates, routing information, parasitic values) while removing unnecessary logic parameters. This parameter transformation enables both fast processing and full design adaptability.
3Manufacturing precision
If full netlist is used for optimization, then complete design information is available and manufacturing precision is improved, but memory utilization increases and processing time increases
Solution Approach 1:
The patent extracts only the essential physical design information (placement, routing, parasitics) from the complete netlist to create a reduced data set. This extraction process removes unnecessary logic details while retaining the critical information needed for optimization, thereby reducing memory utilization while maintaining optimization precision.
Solution Approach 2:
Instead of using the complete netlist and filtering out unnecessary information, the patent inverts the approach by starting with the complete information and explicitly extracting only what is needed. This inversion strategy efficiently reduces memory utilization while preserving all information necessary for manufacturing precision.
4Reliability
If hierarchical optimization is performed with black boxes, then design closure can be achieved, but optimization across block boundaries cannot be performed and design complexity increases
Solution Approach 1:
The patent merges the advantages of hierarchical design (design closure) with full-chip optimization by combining complete netlist data for timing analysis with reduced physical design data for optimization. This merging eliminates the need for complex hierarchical optimization methodologies while achieving both design closure and cross-block optimization.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files. Various embodiments apply to both hierarchical and non-hierarchical designs.