Full-Custom Chip Layout for Mining Algorithm Pipelines
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Solution Overview
Problem
Conventional Auto Place and Route (APR) technology using Electronic Design Automation (EDA) synthesis tools leads to inefficient chip design due to uncontrollable placement relationships and redundancy, especially in complex arithmetic expressions, which hinders the optimization of chip performance.
Innovation Solution
A chip with a full-custom layout is designed using a pipeline structure with uniformly arranged rows of register and logical operation modules, allowing for manual code optimization and direct layout implementation without EDA tools, optimizing performance by reducing redundancy and improving area utilization and critical path length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If Auto Place and Route (APR) technology using EDA synthesis tools is used, then the chip design process is automated, but the placement relationships become uncontrollable and redundant, leading to inferior chip performance
Solution Approach 1:
The chip is divided into multiple operation stages, each containing register modules and logical operation modules arranged in systematic row-column configurations. This segmentation enables precise control over placement relationships while maintaining design efficiency.
Solution Approach 2:
Different regions of the chip are designed with specific functional characteristics - register modules are arranged in arrays with defined row heights, and logical operation modules are positioned adjacently in the Y-direction. This local optimization ensures precise placement relationships in critical areas.
2Ease of manufacture
If conventional APR technology is used, then the design process follows standard automation workflows, but the critical path length increases and performance is hindered
Solution Approach 1:
The module arrangement utilizes two-dimensional spatial optimization with uniform row heights in the X-direction and adjacent positioning in the Y-direction. This dimensional approach shortens the critical path by optimizing signal propagation distances across both axes.
Solution Approach 2:
The uniform row height design and adjacent module positioning are predetermined in the layout phase, allowing optimization of the critical path before actual chip fabrication. This preliminary spatial arrangement minimizes signal transmission delays.
3Productivity
If EDA synthesis tools are used for automatic conversion of RTL code to netlist, then the design process is streamlined, but area utilization becomes inefficient and redundancy increases
Solution Approach 1:
Register modules and logical operation modules are merged into integrated operation stages with systematic row-column arrangements. This merging eliminates redundant spacing and improves area utilization by consolidating functional units into compact, efficient layouts.
Solution Approach 2:
The design employs specific parameter optimizations including uniform row heights, defined array configurations (a rows × b columns for registers, a rows × c columns for logic modules), and adjacent Y-direction positioning. These parameter changes maximize area utilization while maintaining design efficiency.
4Manufacturing precision
If manual code optimization and coding are used for full-custom layout, then chip performance is greatly optimized with smaller area and shorter critical path, but the design process becomes more complex
Solution Approach 1:
The successful full-custom layout approach is replicated through standardized operation stage templates with consistent row-height constraints and module arrangement patterns. This copying mechanism reduces the complexity of manual design by providing reusable design patterns while maintaining optimization benefits.
Data Source
AI summary
The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.