Full Duplex DRAM for Tightly Coupled Compute and Memory Dies
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Solution Overview
Problem
Conventional memory systems face limitations in scaling memory performance due to practical limits in frequency and the number of channels, particularly in traditional half-duplex interfaces, which result in performance penalties from read-write turnarounds and limited bandwidth.
Innovation Solution
The implementation of opportunistic full duplex DRAM architectures with sufficient wires and through-silicon vias (TSVs) to support concurrent memory reads and writes, eliminating the performance penalties of traditional half-duplex interfaces by enabling full duplex memory access operations when channel resources are available.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional half-duplex interfaces are used, then device complexity is reduced, but memory bandwidth and performance are limited due to read-write turnarounds
Solution Approach 1:
The memory interface is segmented into separate read and write channels, allowing independent concurrent operations. Each channel is dedicated to a specific direction (read or write), eliminating the need for turnarounds and enabling full duplex operation without requiring a single shared interface to switch between directions.
Solution Approach 2:
The interface transitions from a single shared bidirectional channel (one dimension) to multiple independent unidirectional channels (adding dimensionality). This dimensional expansion allows simultaneous read and write operations by distributing traffic across multiple parallel paths, effectively resolving the bandwidth limitation while maintaining manageable complexity through modular channel design.
2Productivity
If the number of memory channels is increased, then memory performance improves, but practical limits are reached due to packaging and wiring constraints
Solution Approach 1:
Multiple memory channels are merged into a single package substrate, with compute die and memory die interconnected through integrated wiring and through-silicon vias (TSVs). This merging consolidates what would otherwise require separate physical packages and external wiring into a unified high-density interconnect structure, enabling increased channel count without proportional increases in external wiring complexity.
Solution Approach 2:
The package substrate acts as an intermediary between the compute die and memory die, providing integrated wiring and TSV interconnects that mediate the connection between multiple channels. This intermediary structure absorbs the complexity of multi-channel interconnections, allowing high channel counts to be achieved through the package-level interconnect architecture rather than through cumbersome external wiring.
3Speed
If frequency is increased to improve performance, then processing speed improves, but practical limits are reached due to signal integrity and timing constraints
Solution Approach 1:
Memory operations are initiated and prepared in advance through the integrated memory controller, with read and write commands scheduled and executed concurrently through dedicated channels. This preliminary action approach allows the system to maintain high effective throughput by pre-positioning operations in the command queue and executing them in parallel, achieving high performance without requiring excessively high clock frequencies that would compromise signal integrity.
Data Source
AI summary
Methods and apparatus for opportunistic full duplex DRAM for tightly coupled compute die and memory die. A memory controller includes one or more memory channel input-output (IO) interfaces having sets of read data (RdDQ) lines and write data (WrDQ) lines, and includes logic to implement concurrent read and write operations utilizing the RdDQ lines and WrDQ lines. A memory channel IO interface may be coupled to one or more memory devices such as DRAM DIMMs or DRAM/SDRAM dies having a mating IO interface, such as using through-silicon vias (TSVs) and die-to-die interconnects. Circuitry in a memory device or die includes a macro block of IO drivers coupled to the memory channel IO circuitry via a macro interface supporting full duplex operations. IO drivers in a macro block may be connected to memory banks using half-duplex bi-direction links to different banks or full duplex links to the same bank.