High-speed full-duplex transceiver and method thereof
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Solution Overview
Problem
Existing high-speed full-duplex transceiver circuits face challenges in effectively suppressing echo noise and addressing signal dispersion, which impairs receiver performance, particularly in hybrid circuits that are not amenable to high-speed applications.
Innovation Solution
The proposed transceiver design incorporates a digital-to-analog converter (DAC) for both signal transmission and echo cancellation, utilizing shunt resistors, DC coupling resistors, an AC coupling capacitor, a transimpedance amplifier, and an inductive load to interface with communication media, effectively canceling echo and equalizing signal dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a hybrid circuit with active filter and ratio converter is used for echo suppression, then echo cancellation is achieved, but the circuit is not amenable to high-speed applications
Solution Approach 1:
The patent replaces traditional analog echo suppression circuits (active filters, ratio converters, operational amplifiers) with a digital echo cancellation system. The transmitter digital signal processor generates an echo signal by processing the transmit signal through a digital filter, which is then subtracted from the received signal in the receiver digital signal processor. This substitution of digital processing for analog circuitry enables high-speed operation while maintaining effective echo cancellation.
Solution Approach 2:
The patent changes the operating parameters from analog domain to digital domain. By implementing echo cancellation in the digital realm using programmable digital signal processors and digital filters, the system achieves both effective echo suppression and compatibility with high-speed applications. The digital implementation allows for flexible parameter adjustment and optimization for high-speed operation.
2Ease of operation
If a hybrid circuit with operational amplifier is used for signal processing, then signal processing function is achieved, but the circuit is not amenable to high-speed applications
Solution Approach 1:
The patent replaces operational amplifiers and analog signal processing circuits with digital signal processing implementations. The transmitter digital signal processor and receiver digital signal processor perform all necessary signal processing functions digitally, eliminating the speed limitations of operational amplifiers while maintaining full signal processing capability.
3Reliability
If equalization circuit is added to address signal dispersion, then signal quality is improved, but device complexity increases
Solution Approach 1:
The patent combines the equalization function with the existing digital signal processing architecture. The transmitter digital signal processor applies equalization to the transmit signal, and the receiver digital signal processor applies equalization to the received signal. By integrating equalization into the digital signal processing path rather than adding separate analog equalization circuits, the patent improves signal quality while minimizing additional complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves efficient echo cancellation and signal equalization, enabling high-speed full-duplex communication without the need for operational amplifiers, thus supporting high-speed applications.
Implementation Method 1
a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node
Implementation Method 2
an AC (alternate current) coupling capacitor configured to couple the third node to a fourth node
Implementation Method 3
a first shunt resistor configured to shunt the first node to a DC (direct current) node; a second shunt resistor configured to shunt the second node to a DC node
Data Source
AI summary
A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.