Full-Duplex Memory With Separate Read/Write Paths
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Solution Overview
Problem
Existing memory systems face challenges in achieving high-performance and high-capacity due to limitations in interface technologies, such as bidirectional interfaces leading to low bandwidth and high latency, and unidirectional interfaces not supporting stacked memory components, resulting in tradeoffs between performance and capacity.
Innovation Solution
A full duplex memory system with separate read and write paths using unidirectional interfaces, enabling concurrent reading and writing to multiple ranks of memory components, thereby eliminating bus turnaround time constraints and enhancing bandwidth and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If bidirectional interfaces are used, then memory components can be accessed for reading and writing, but bandwidth is reduced and latency is increased due to bus turnaround time constraints
Solution Approach 1:
The patent divides the interface into separate read-only and write-only paths, segmenting the bidirectional communication into independent unidirectional channels. This allows simultaneous read operations on one path and write operations on another path without interference, eliminating bus turnaround time constraints and increasing bandwidth.
Solution Approach 2:
The patent transitions from a single bidirectional interface to multiple unidirectional interfaces by adding a dimensional separation between read and write operations. This dimensional change enables concurrent operations that were previously mutually exclusive, thereby increasing productivity without sacrificing adaptability.
2Productivity
If unidirectional interfaces are used, then bandwidth is improved, but stacked memory components cannot be supported
Solution Approach 1:
The patent implements a memory system with multiple channels, each capable of supporting both read and write operations through separate unidirectional interfaces. This universal design allows the system to accommodate stacked memory components while maintaining high bandwidth performance, as each channel can independently handle read/write operations without requiring bidirectional switching.
3Quantity of substance
If stacked memory components are implemented, then capacity is increased, but interface limitations reduce performance
Solution Approach 1:
The patent segments the memory interface into multiple independent channels with separate read and write paths. This segmentation allows stacked memory components to be accessed simultaneously through different channels without performance degradation, as each channel operates independently with dedicated read/write paths, thereby maintaining high performance while increasing capacity.
Data Source
AI summary
In some implementations, a memory device may receive a read command instructing the memory device to read a first set of host data stored at a memory component that is associated with a memory component rank, of multiple memory component ranks associated with a channel. The memory device may read, via the channel based on receiving the read command, the first set of host data using a read-only interface associated with the memory component. The memory device may receive a write command instructing the memory device to write a second set of host data to the memory component. The memory device may write, via the channel and based on receiving the write command, the second set of host data to the memory component using a write-only interface associated with the memory component.