Full-Duplex RF Sampler Using Zero-Crossing Timing Extraction

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Solution Overview

Problem

Full-duplex systems face significant self-interference challenges due to the sharing of RF resources, particularly in high-power systems, where electrical balance-based cancellation techniques result in high insertion loss and narrowband operation, and direct sampling of RF signals is complicated by charge injection, clock feed-through, and signal feed-through.

Innovation Solution

A sampler that clips amplitude information from coupled transmitter and antenna port voltages to perform time-selective sampling at transmitter zero-crossings, using a phase detector to determine time delay and a current integrator to generate a sampled output, exploiting implicit voltage-to-delay conversion for wide-bandwidth operation without requiring a high linearity receiver frontend.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If electrical balance-based self-interference cancellation techniques are used in high-power systems, then self-interference cancellation is achieved, but insertion loss increases and bandwidth becomes narrow

Engineering Contradiction:
Improveself-interference cancellationVSAvoidinsertion loss
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts only the zero-crossing timing information from the transmitter signal using a buffer that clips amplitude information. This extracted timing information is then used to control the sampling operation, separating the timing extraction function from the full signal processing path and avoiding the insertion loss associated with electrical balance techniques.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the electrical balance-based cancellation mechanism with a time-selective sampling mechanism. Instead of using electrical components that introduce insertion loss, the system uses timing-based control where the buffer extracts zero-crossing moments and the sampler captures received signal samples at these specific instants, substituting electrical cancellation with temporal selection.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If electrical balance-based self-interference cancellation techniques are used, then self-interference cancellation is achieved, but operational bandwidth becomes narrow

Engineering Contradiction:
Improveself-interference cancellationVSAvoidbandwidth
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The buffer extracts only the essential zero-crossing timing information from the transmitter signal, discarding amplitude information. This extracted timing signal serves as a control reference that is independent of the signal bandwidth, allowing the system to achieve self-interference cancellation across wide bandwidths without being constrained by narrowband electrical balance techniques.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The time-selective sampling mechanism dynamically adapts to the transmitter signal's zero-crossing instants, which occur at different times for different frequency components. This dynamic timing-based approach allows the system to handle wide bandwidth signals effectively, as each frequency component is sampled at its appropriate zero-crossing moment, providing inherent wideband capability.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If direct sampling of received RF signal is performed, then sampling simplicity is achieved, but charge injection and clock feed-through errors occur

Engineering Contradiction:
Improvesampling structureVSAvoidsampling accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The system performs preliminary action by extracting the zero-crossing timing information from the transmitter signal before the sampling operation. The buffer clips the transmitter signal to generate a timing reference that indicates when the transmitter signal is at zero crossing. This preliminary timing extraction allows the sampler to capture received signal samples at the optimal moments when self-interference is minimized, compensating for the inherent errors in direct sampling without requiring complex correction circuits.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If time selective sampling is used to recover received RF signal, then self-interference elimination is achieved, but implementation challenges arise due to charge injection, clock feed-through and signal feed-through

Engineering Contradiction:
Improveself-interference eliminationVSAvoidimplementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent takes out only the essential timing information from the transmitter signal using a simple buffer that clips amplitude information. This extracted timing signal is then used to control the sampling operation. By extracting only the necessary timing information and using it to control a simple sampler, the system achieves time-selective sampling without requiring complex implementation circuits, thereby avoiding charge injection, clock feed-through, and signal feed-through problems associated with more complex time-selective sampling implementations.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11303320B2Sampler in a full-duplex system and method of sampling received signal
Publication Date: 2022.04.12 INDIAN INST OF TECH MADRAS
  • US11303320B2 patent drawing
  • US11303320B2 patent drawing
  • US11303320B2 patent drawing

AI summary

According to the embodiment discloses a method providing direct RF sampling of the received signal in a full duplex system. A sampler in the full-duplex system comprises a buffer to clip an amplitude information from each of a coupled transmitter (Tx) signal and a voltage at an antenna port of the sampler for obtaining a buffered transmitter signal and a buffered voltage at the antenna port. Phase detector in the sampler is configured to perform sampling of time delay between the buffered transmitter signal and the voltage at the antenna port and generate an output. The sampler further comprises current integrator configured to pass the output of the phase detector for generating a sampled output, wherein the sampled output generates an output received signal.