Full-duplex Self-interference Cancellation via Impulse Response Estimation
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Solution Overview
Problem
Wireless communication systems face challenges in self-interference cancellation, particularly when using full-duplex radios that transmit and receive signals on the same frequency band, as existing methods require additional circuit elements and increased computational complexity, especially with multiple antennas.
Innovation Solution
A processor estimates the impulse response of the full-duplex radio by transmitting periodic signals and determining the difference between received and estimated signals, allowing for self-interference cancellation without additional digital cancellation circuits or precise timing, thereby reducing computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuit elements are used to reduce interference, then self-interference cancellation is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent extracts the self-interference cancellation function from separate dedicated circuit elements and integrates it into the existing transceiver processing chain. By using the existing analog-to-digital converters and digital signal processors to perform cancellation, the solution removes the need for additional specialized hardware circuits, thereby reducing device complexity while maintaining cancellation effectiveness
Solution Approach 2:
The patent makes the existing transceiver components multi-functional by having them perform both their primary functions (signal transmission/reception) and the additional function of self-interference cancellation. The digital signal processor, already present for signal processing, is also used to execute cancellation algorithms, eliminating the need for dedicated cancellation hardware
2Adaptability or versatility
If the number of antennas is increased, then wireless communication capability is improved, but computational time for interference identification increases
Solution Approach 1:
The patent performs preliminary characterization of the self-interference channel by transmitting known test signals and measuring the channel response in advance. This pre-computed channel information is stored and then used during normal operation to quickly cancel interference without performing complex real-time computations, thereby reducing computational time while supporting multiple antennas
Solution Approach 2:
The patent uses a simplified digital cancellation model that processes only the essential components of self-interference cancellation. Rather than performing complete signal inversion or using complex adaptive algorithms, the system applies a streamlined approach that computes interference compensation based on pre-characterized channel responses, achieving effective cancellation with reduced computational complexity
Data Source
AI summary
This disclosure describes methods and devices related to self-interference cancellation. A device is disclosed comprising: at least one memory storing computer-executable instructions; and at least one processor configured to access the at least one memory, wherein the at least one processor may be configured to execute the computer-executable instructions to cause to send at least one first symbol sequence at least twice on a first transmit chain and at least one second symbol sequence twice on a second transmit chain. The processor may be configured to execute the computer-executable instructions to determine at least one third symbol sequence at least twice on a first receive chain and at least one fourth symbol sequence at least twice on a second receive chain. The processor may be configured to execute the computer-executable instructions to determine a first impulse response of a first power amplifier on the first transmit chain and a second impulse response of a second power amplifier on the second transmit chain. The processor may be configured to execute the computer-executable instructions to determine a first aggregate impulse response associated with one or more first devices on the first transmit chain and the first receive chain. The processor may be configured to execute the computer-executable instructions to determine a second aggregate impulse response associated with one or more second devices on the second transmit chain and the second receive chain. The processor may be configured to execute the computer-executable instructions to determine a third impulse response based at least in part on the first and second impulse response, and the first and second aggregate impulse response. The processor may be configured to execute the computer-executable instructions to determine an estimate of the third impulse response based at least in part on the at least one first symbol sequence or the at least one second symbol sequence.