Fully Aligned Interconnects via Selective Area Deposition
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Solution Overview
Problem
The fabrication of fully aligned vias in semiconductor integrated circuits faces challenges such as misalignment errors leading to increased line resistance, capacitance, and reduced electromigration reliability, which limit the downscaling of semiconductor devices.
Innovation Solution
A method involving the formation of a sacrificial dielectric layer and metal cap on copper lines, followed by selective removal of the sacrificial dielectric and cap to create fully aligned vias without increasing copper line thickness, thereby eliminating shorting risks and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography alignment methods are used, then manufacturing process simplicity is maintained, but overlay errors cause misalignment between via features and metal lines leading to increased resistance and reduced reliability
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial dielectric layer and metal cap structure before via formation. The metal cap is deposited on the metal line top surface, and the sacrificial dielectric is formed over it. This preliminary structure enables self-aligned via formation without requiring complex lithography alignment, as the via automatically aligns to the metal line through the sacrificial structure that is removed later.
Solution Approach 2:
The patent uses an intermediary approach by introducing a sacrificial dielectric layer and metal cap as temporary structures that mediate between the metal line and the final via structure. These intermediary elements facilitate precise via alignment during fabrication, and are subsequently removed to leave the fully aligned via. This intermediary structure eliminates the need for complex lithography alignment while achieving high precision.
2Reliability
If copper line thickness is increased to compensate for misalignment, then resistance is reduced, but fabrication process complexity increases and shorting risks arise
Solution Approach 1:
The patent employs a selective removal process analogous to pneumatic/hydraulic principles where a sacrificial structure (metal cap and dielectric) is used to create a precisely defined cavity that is then filled with conductive material. The sacrificial structure acts as a template that ensures proper via dimensions and alignment without requiring increased copper line thickness, thereby maintaining reliability while avoiding shorting risks.
Solution Approach 2:
The patent changes the fabrication parameters by transitioning from direct lithography alignment to a self-aligned approach using sacrificial structures. This parameter change allows via formation with precise dimensional control without increasing copper thickness, thereby maintaining electromigration reliability while simplifying the fabrication process and eliminating shorting risks associated with thicker lines.
3Manufacturing precision
If advanced lithography techniques with phase-shifting masks are employed, then via printing latitude is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent extracts the alignment function from the lithography process itself and transfers it to a self-aligned structural approach. Instead of relying on advanced lithography techniques like phase-shifting masks to achieve alignment, the invention removes the alignment dependency from lithography by using sacrificial dielectric and metal cap structures that automatically define via positions, thereby improving via printing latitude while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables robust, fully aligned copper vias with reduced resistance-capacitance delay and enhanced electromigration reliability without complicating the fabrication process.
Implementation Method 1
selective removal of the sacrificial dielectric and cap to create fully aligned vias
Implementation Method 2
An interconnect structure is deposited such that at least a portion of the interconnect structure fills the trench, thereby defining a fully aligned top via
Data Source
AI summary
Interconnect structures and methods for forming the interconnect structures generally include forming a dielectric layer over a substrate. The dielectric layer includes a dielectric layer top surface. A metal line is formed in the dielectric layer. The metal line includes a sacrificial upper region and a lower region. The sacrificial upper region is formed separately from the lower region and the lower region includes a lower region top surface positioned below the dielectric layer top surface. The sacrificial upper region is removed, thereby exposing the lower region top surface and forming a trench defined by the lower region top surface and sidewalls of the dielectric layer. An interconnect structure is deposited such that at least a portion of the interconnect structure fills the trench, thereby defining a fully aligned top via.