Fully Aligned Via Dual Metallization Resistance Reduction
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Solution Overview
Problem
Current fabrication processes for fully aligned vias in semiconductor structures result in reduced conductor material volume in larger features, increasing overall resistance due to the same formation methods being used for both minimum ground rule and larger sized features.
Innovation Solution
The method involves forming recessed conductive structures with alternative metal materials in minimum width features and filling wider features with conductor material, while maintaining the alternative metal in minimum width features to reduce resistance, allowing for dual metallization and improved via and interconnect resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same formation method is used for both minimum ground rule and larger sized features, then the fabrication process is simplified, but the conductor material volume in larger features is reduced, increasing overall resistance
Solution Approach 1:
The fabrication process is segmented into separate treatment paths for minimum ground rule features and larger sized features. Minimum ground rule features undergo recessing of the first conductive material, while larger features are filled with a second conductive material without recessing, allowing optimized resistance characteristics for each feature type
Solution Approach 2:
Different conductive materials and processing treatments are applied to different regions based on feature size. Larger features receive full-volume second conductive material for low resistance, while minimum ground rule features use recessed first conductive material with dielectric fill for isolation, creating locally optimized structures
2Manufacturing precision
If recessed conductive structures are formed in minimum width features, then via alignment and electrical contact are improved, but the conductor material volume in wider lines is reduced, increasing resistance
Solution Approach 1:
The conductive structures are segmented by feature size: minimum width features have recessed first conductive material for precise via alignment, while wider features are completely filled with second conductive material to maintain low line resistance, with each segment optimized for its specific function
Solution Approach 2:
Instead of applying the same recessing treatment to all features, the invention inverts the approach by filling wider features completely with second conductive material while only recessing minimum width features, thereby achieving both precise via alignment and low line resistance
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.