Fully Aligned Via Interconnects with Partial Etch Stop Removal
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Solution Overview
Problem
In the fabrication of silicon-based devices, the formation of fully aligned vias (FAVs) in BEOL processing faces challenges such as alignment issues and increased capacitance due to the presence of etch stop layers within low-k dielectric materials, which affect the reliability and performance of interconnect structures.
Innovation Solution
The method involves depositing a conformal dielectric etch stop layer, removing portions adjacent to metal lines where vias are not formed, and dual damascene patterning to create vertically aligned vias, thereby reducing the area of the etch stop layer and minimizing capacitance while ensuring electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conformal dielectric etch stop layer is deposited over the entire surface including adjacent to all metal lines, then the etch stop layer provides complete protection during processing, but the area of the etch stop layer increases causing increased parasitic capacitance
Solution Approach 1:
The etch stop layer is segmented into discrete portions rather than being continuous. Etch stop layer portions are formed only adjacent to selected metal lines where vias will be created, while removing portions adjacent to metal lines where vias will not be formed. This segmentation maintains necessary protection zones while eliminating unnecessary capacitance-contributing areas.
Solution Approach 2:
The etch stop layer is selectively present only in locations where it is needed - adjacent to metal lines that will have vias formed next to them. The local quality of the etch stop layer is optimized by having it only where it serves a functional purpose (protecting during via etching) and removing it where it would only contribute to parasitic capacitance.
2Object-affected harmful factors
If the etch stop layer area is reduced by removing portions adjacent to metal lines where vias are not formed, then parasitic capacitance is minimized, but processing protection is reduced
Solution Approach 1:
The etch stop layer is divided into discrete segments positioned only where needed - adjacent to metal lines that will have vias formed beside them. This segmentation maintains processing protection exactly where required while eliminating protection (and capacitance) where not needed.
Solution Approach 2:
Unnecessary portions of the etch stop layer are extracted and removed - specifically those adjacent to metal lines where vias will not be formed. This extraction eliminates the harmful parasitic capacitance contribution while preserving the essential processing protection function where it is actually needed.
3Reliability
If fully aligned vias are formed to maximize contact area with metal lines, then via resistance is reduced, but alignment precision requirements increase
Solution Approach 1:
The etch stop layer portions are formed in advance, adjacent to the selected metal lines, before the via formation process. This preliminary positioning of the etch stop layer serves as a guide and protection mechanism that facilitates precise via alignment with the metal lines, reducing the actual alignment precision burden during the via etching step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of FAV interconnects by reducing via resistance and improving time-dependent dielectric breakdown properties, while limiting parasitic capacitance and enhancing breakdown voltage.
Implementation Method 1
depositing a conformal dielectric etch stop layer over a bottom interlevel dielectric layer
Implementation Method 2
dual damascene patterning the top interlevel dielectric layer. This patterning forms one or more top trenches within the top dielectric layer and one or more vias extending downwardly from each of the one or more top trenches
Implementation Method 3
depositing interconnect metal within the one or more top trenches, the one or more vias, and the trenches containing the second subset of the metal lines
Data Source
AI summary
A dual damascene interconnect structure with a fully aligned via integration scheme is formed with a partially removed etch stop layer. Portions of the etch stop layer are removed prior to dual damascene patterning of an interlevel dielectric layer formed above metal lines and after such patterning. Segments of the etch stop layer remain only around the vias, allowing the overall capacitance of the structure to be reduced.