Fully Aligned Vias via Subtractive Patterning for CMOS Interconnects
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Solution Overview
Problem
Conventional dual damascene fabrication processes result in reduced performance characteristics due to misalignment of vias with metal lines, leading to increased resistivity and decreased contact area, which is exacerbated by the scaling demands of modern CMOS technology.
Innovation Solution
A novel subtractive patterning process is employed to form fully aligned vias between lower and upper metal strips, ensuring all sides of the via are co-planar with the metal strips, thereby improving alignment and contact area and reducing interconnect resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dual damascene fabrication process is used, then manufacturing process is simpler, but via alignment with metal lines deteriorates leading to increased resistivity
Solution Approach 1:
Instead of forming vias first and then metal lines (conventional approach), this patent forms metal lines first and then uses them as etch masks to define via locations. The via formation process is inverted to occur after metal line deposition, ensuring automatic alignment and eliminating the alignment problems inherent in the conventional sequence.
Solution Approach 2:
The metal lines are formed in advance before via formation. These pre-formed metal lines serve as etch masks that automatically define the precise locations where vias should be formed, ensuring proper alignment is achieved before the via formation step begins.
2Manufacturing precision
If via size is reduced to meet scaling demands, then device density increases, but contact area with metal lines decreases leading to increased resistivity
Solution Approach 1:
The metal lines themselves serve as the etch mask for defining via locations. This self-service approach ensures that the via formation is automatically aligned with the metal lines, eliminating alignment errors and ensuring maximum contact area between vias and metal lines even as dimensions are scaled down.
Solution Approach 2:
By inverting the conventional sequence and forming metal lines before vias, the patent ensures that via locations are automatically determined by the metal line geometry, guaranteeing proper alignment and adequate contact area regardless of the scaling dimension.
3Ease of manufacture
If additive damascene or dual damascene process is used, then interconnect structures can be formed, but via misalignment occurs leading to decreased contact area and increased resistivity
Solution Approach 1:
The patent inverts the conventional damascene sequence by forming metal lines first and then using them as masks for via formation. This reversal eliminates the alignment problems inherent in additive and dual damascene processes, achieving precise via-to-metal-line alignment while maintaining ease of manufacture.
Solution Approach 2:
The metal lines serve as an intermediary element that simultaneously functions as both the interconnect structure and the etch mask for via formation. This dual role of the metal lines as both functional element and patterning tool ensures precise alignment without requiring separate mask layers.
Data Source
AI summary
An interconnect structure includes an interlayer dielectric (ILD) having a cavity extending therethrough along a first direction. A first electrically conductive strip is formed on a substrate and within the cavity. The first electrically conductive strip extends along the first direction and across an upper surface of the substrate. A second electrically conductive strip is on an upper surface of the ILD and extends along a second direction opposite the first direction. A fully aligned via (FAV) extends between the first and second electrically conductive strips such that all sides of the FAV are co-planar with opposing sides of the first electrically conductive strip and opposing sides of the second electrically conductive strip thereby providing a FAV that is fully aligned with the first electrically conductive strip and the second electrically conductive strip.