Fully-Depleted SON Device With Etched Floating Dielectric
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Solution Overview
Problem
Conventional silicon-on-nothing (SON) devices face issues with dopant segregation and leakage current due to their structure, leading to suboptimal performance in downscaled semiconductor technology, particularly for gate lengths less than 25 nm, where thickness variation causes Vt roll-off and sub-threshold slope variability.
Innovation Solution
A fully-depleted SON device is developed with an undoped-SON on an undoped-thin-SOI substrate, where the floating dielectric region is etched back to minimize dopant segregation, eliminating the need for well implants and reducing off-state current, by creating a void filled with dielectric material and forming a source and drain junction on a silicon-on-insulator layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional SON devices are used with source and drain on bulk substrate, then device structure is simple, but significant leakage current occurs below the insulator layer
Solution Approach 1:
The patent removes the bulk substrate beneath the insulator layer to eliminate the source of leakage current. By extracting the problematic bulk substrate region and replacing it with a suspended structure, the harmful leakage current path is eliminated while maintaining the essential device functionality.
Solution Approach 2:
The patent transitions from a conventional planar structure with bulk substrate to a three-dimensional suspended structure where the insulator layer is elevated above the substrate. This dimensional change creates a cavity beneath the insulator, eliminating the leakage path while providing new spatial relationships for device optimization.
2Ease of manufacture
If conventional SON devices are used, then fabrication process is straightforward, but dopant segregation occurs in the floating dielectric resulting in lower effective dose and higher extension region resistance
Solution Approach 1:
The patent performs dopant implantation into the extension region before the floating dielectric is formed. By executing the doping action in advance, before the dielectric material is deposited, the dopants are properly incorporated into the semiconductor region without being blocked or segregated by the subsequent dielectric layer formation.
Solution Approach 2:
The patent inverts the conventional sequence of operations by forming the extension region and performing dopant implantation before creating the floating dielectric structure. This reversed sequence eliminates the dopant segregation problem that occurs when dielectric is formed first, as the dopants are introduced into the semiconductor material directly without interference from the dielectric layer.
3Manufacturing precision
If ETSOI devices are used, then thickness control is improved, but Vt roll-off and sub-threshold slope variability occur for gate length less than 25 nm
Solution Approach 1:
The patent changes the structural parameters by transitioning from a fully suspended ETSOI structure to a hybrid structure where only the channel region is suspended while source and drain remain on the substrate. This parameter change in the device architecture eliminates the thickness variation problems that cause Vt roll-off in fully suspended structures for short gate lengths.
Solution Approach 2:
The patent applies different structural configurations to different regions of the device: the channel region maintains a suspended structure for excellent electrostatic control, while the source and drain regions remain on the substrate for mechanical stability and reduced leakage. This local differentiation optimizes each region's properties for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved short-channel characteristics, reduced Vt roll-off, and lower off-state current, enhancing the performance and reliability of semiconductor devices at smaller scales.
Implementation Method 1
growing a first epitaxial layer on the substrate, growing a second epitaxial layer on the first epitaxial layer
Implementation Method 2
filling the void with a dielectric material
Data Source
AI summary
A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.