Function Estimation Hardware Using Higher-Order Polynomial Convergence
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Solution Overview
Problem
Existing hardware logic for evaluating functions like the reciprocal, square root, or cube root of an input number using iterative methods introduces rounding errors that accumulate and requires multiple iterations, leading to inefficiencies in throughput and hardware size.
Innovation Solution
Implementing a function estimation hardware logic unit with a combination of multipliers and adders to perform an mth-order polynomial convergence, where m is not equal to two, to quickly refine estimates of these functions, reducing the number of iterations needed and minimizing rounding errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If iterative methods are used to evaluate functions in hardware, then the same hardware can be reused for multiple iterations, but rounding errors accumulate and multiple iterations are required
Solution Approach 1:
The patent changes the convergence order parameter from traditional quadratic (m=2) to higher orders (m>2) by modifying the polynomial approximation degree. This allows the hardware to achieve faster convergence with fewer iterations, reducing accumulated rounding errors while maintaining hardware reuse efficiency
Solution Approach 2:
The patent replaces standard iterative approximation mechanisms with a higher-order polynomial-based iteration mechanism. By substituting the conventional iteration approach with an mth-order polynomial method, the system achieves faster convergence rates without requiring additional hardware resources
2Measurement precision
If multiple iterations are performed to improve accuracy, then the function estimate becomes more precise, but the throughput decreases
Solution Approach 1:
The patent modifies the iteration parameter by implementing mth-order convergence where m>2. This parameter change enables the system to achieve high precision with fewer iterations, thereby maintaining high throughput while improving accuracy
Solution Approach 2:
The patent optimizes the iteration process by reducing the number of periodic iteration cycles required. Through higher-order polynomial convergence, the system achieves the desired precision in fewer periodic actions, improving overall throughput
3Area of stationary object
If standard iterative hardware is used, then the hardware size is reduced, but the number of iterations increases leading to more rounding errors
Solution Approach 1:
The patent creates a universal hardware unit that can perform both the input processing and the higher-order polynomial calculations within a single integrated structure. This multi-functional design achieves fast convergence with fewer iterations while maintaining compact hardware size
Solution Approach 2:
The patent combines multiple functions (input reception, polynomial calculation, and output generation) into a single integrated hardware unit. By merging these functions, the system achieves efficient mth-order convergence without increasing overall hardware footprint
Data Source
AI summary
A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by1/di.The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.