Automatic Functional Coverage Extraction for Emulation Verification
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Solution Overview
Problem
Current circuit design verification methods are inefficient in finding design errors, especially in complex circuits with billions of transistors, as they do not scale well and are costly, leading to a need for improved techniques that maximize coverage while maintaining low costs.
Innovation Solution
A method involving multiple verification stages using different test benches, with the first stage employing hardware emulation and the second stage using simulation, to generate and compare functional coverage, and automatically generate cover property statements to enhance coverage if necessary, thereby ensuring equal or greater coverage in subsequent verification runs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional test bench verification methods are used, then verification can be performed with simple setup, but verification efficiency and error detection capability deteriorate for complex circuits
Solution Approach 1:
The patent implements feedback by automatically generating cover property statements based on the difference between emulation coverage and simulation coverage. The system monitors coverage metrics during verification and uses this feedback to dynamically generate additional test sequences that target uncovered functional areas, thereby improving verification efficiency for complex circuits
Solution Approach 2:
The patent performs preliminary hardware emulation to establish a baseline functional coverage before proceeding to simulation. By pre-executing critical verification paths in hardware emulation and capturing the coverage achieved, the system prepares advance guidance for the subsequent simulation phase, enabling more targeted and efficient verification of complex circuit behaviors
2Reliability
If extensive analysis and verification methods are used to ensure circuit operation, then verification accuracy improves, but verification cost and time increase
Solution Approach 1:
The patent segments the verification process into two distinct phases: hardware emulation phase and simulation phase. Each phase has specific objectives and generates different types of coverage data. This segmentation allows the system to leverage the speed of simulation for most verification while using hardware emulation for critical path validation, thereby maintaining high verification accuracy without proportionally increasing verification time
Solution Approach 2:
The patent applies partial action by using hardware emulation selectively only for establishing baseline coverage of critical functional paths, rather than performing exhaustive emulation of all circuit behaviors. The majority of verification is then performed through simulation guided by the partial coverage data from emulation, reducing overall verification time while maintaining reliability through targeted use of high-accuracy emulation
3Measurement precision
If hardware emulation is used for verification, then functional coverage accuracy improves, but resource consumption and cost increase
Solution Approach 1:
The patent creates a virtual model (simulation environment) that replicates the circuit behavior observed in hardware emulation. By copying the essential functional characteristics and coverage metrics from the hardware emulation phase into the simulation phase, the system maintains measurement precision while enabling resource-efficient re-verification and analysis without requiring continuous hardware emulation resources
Data Source
AI summary
A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the circuit design using a second test bench to generate a second functional coverage, comparing the second functional coverage to the first functional coverage, and automatically generating one or more cover property statements if the second functional coverage is less than the first functional coverage. The one or more cover property statements cause the second functional coverage to become equal to or greater than the first functional coverage.