Functional Descriptor DMA Control for Non-Contiguous Memory Transfer
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Solution Overview
Problem
Conventional DMA controllers struggle with moving data between non-contiguous memory locations, requiring large descriptor tables and frequent CPU intervention, which impacts system throughput.
Innovation Solution
A DMA controller system utilizing functional descriptors and pattern matching circuits to manage data transfer between non-contiguous memory blocks independently of the CPU, using trigger configuration registers and address/count registers to control data transfer without large descriptor tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DMA controllers use descriptor tables to manage non-contiguous data blocks, then data movement between non-contiguous memory locations is enabled, but large descriptor tables must be built by the CPU increasing device complexity and CPU overhead
Solution Approach 1:
The patent extracts the descriptor table management function from the CPU and relocates it to the DMA controller itself. The DMA controller now autonomously builds and manages its own descriptor tables without CPU intervention, eliminating the complexity burden from the CPU while maintaining support for non-contiguous data blocks.
Solution Approach 2:
The DMA controller performs self-service by automatically constructing descriptor tables based on scatter-gather list entries provided by the CPU. Once initialized, the DMA controller independently manages its own descriptor tables during data transfer operations, freeing the CPU from the complexity of descriptor table maintenance.
2Ease of operation
If CPU polls status bits to control operational flow, then flow control is achieved, but system throughput is reduced due to frequent CPU intervention
Solution Approach 1:
The DMA controller implements self-service flow control by autonomously monitoring status bits and managing its own operational flow. The controller independently determines when data transfers should pause or continue based on status conditions, eliminating the need for continuous CPU polling and intervention.
Solution Approach 2:
The system implements feedback mechanisms where the DMA controller continuously monitors status bits and adjusts its operation accordingly. This closed-loop feedback allows the DMA controller to autonomously manage flow control based on real-time system conditions without CPU involvement.
3Adaptability or versatility
If frequent CPU intervention is used for data movement control, then operational flexibility is maintained, but CPU overhead increases impacting overall system performance
Solution Approach 1:
The patent extracts flow control responsibilities from the CPU and transfers them to the DMA controller. The DMA controller now independently manages operational flexibility through autonomous status monitoring and flow decision-making, eliminating the time-consuming CPU intervention while maintaining system adaptability.
Data Source
AI summary
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.