Functional Test Pattern Generation for VLSI Diagnostics
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Solution Overview
Problem
The generation of effective functional test patterns for diagnostics and characterization in chip manufacturing is complex due to the rapid densification of VLSI devices with diverse integrated circuit functions, requiring test patterns that emulate system mission mode environments, which existing methods fail to address effectively.
Innovation Solution
A method and system for generating functional test patterns involve receiving verification sequences from a design verification tool, executing them against a device to capture traces, processing these traces to generate emulated test patterns in a tester-independent format, and then processing these patterns using a tester-specific post-processor to create functional test patterns compatible with automatic test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If verification sequences are executed against highly integrated VLSI devices to generate functional test patterns, then system design verification and device quality are ensured, but the complexity of generating effective test patterns increases due to diverse integrated circuit functions
Solution Approach 1:
The test pattern generation process is segmented into distinct functional modules: a design verification tool module that receives verification sequences, a functional exerciser module that executes them against the device, a trace processor module that captures and processes traces, and a test pattern generator module that creates final test patterns. This segmentation allows each module to handle specific aspects of the complex generation process independently, managing overall system complexity while ensuring device quality through systematic verification.
2Measurement precision
If functional test patterns emulate system mission mode environments, then effective diagnostics and characterization are achieved, but the time and computational resources required for test execution increase
Solution Approach 1:
The system performs preliminary actions by executing verification sequences against a device model or simulation environment before actual device testing. The design verification tool module receives verification sequences and executes them to generate expected behavior traces in advance. This preliminary execution allows the trace processor module to compare actual device traces against pre-established expected behavior, achieving precise diagnostics without requiring exhaustive real-time testing of all system mission modes.
Solution Approach 2:
The system creates copies of system mission mode environments through verification sequences that model expected device behavior. Instead of requiring actual system mission execution, the functional exerciser module executes verification sequences that replicate critical system operations, generating traces that represent normal and abnormal system behavior. This copying approach enables precise measurement and diagnostics while significantly reducing test execution time compared to actual system operation.
3Adaptability or versatility
If traces are captured and processed in emulation compatible format, then tester independence is achieved, but additional processing steps are required to convert to tester-specific formats
Solution Approach 1:
The trace processor module serves as an intermediary that converts traces from the functional exerciser module into emulation compatible format, which acts as a universal intermediate representation. This intermediary format enables tester independence by allowing traces to be processed without being tied to specific test equipment. The processing system then includes a test pattern generator module that converts the emulation compatible traces into tester-specific formats as needed, achieving adaptability to multiple testers while managing processing complexity through standardized intermediate representation.
Data Source
AI summary
A computer system verifies functional test patterns for diagnostics, characterization and manufacture testing. The system generates, by a system designer, verification sequences including initial trace traces selected from a verification sequence data to test system functional design. The system includes a trace module, an emulated pattern generator module, and a test pattern verification and debug module. The trace module adds custom information to the traces to generate modified traces and the system executes the verification sequences against a device to generate traces. The trace module further processes the modified traces by parsing the captured modified traces. The system verifies data integrity and summarizes statistics of the captured traces. The emulated pattern generator module generates emulated test patterns, which are based on the output of the trace module and have independent format streams compatible with a device test port. The test pattern verification and debug module verifies the emulated test patterns.