Funnel-Shaped Vias in Multilevel Interconnects
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Solution Overview
Problem
Current multilevel interconnect structures face challenges in miniaturization due to high electrical resistance in vias filled with tungsten, leading to power dissipation issues and potential device damage, especially in high-current applications like Bipolar-CMOS-DMOS devices.
Innovation Solution
The development of multilevel interconnect structures with funnel-shaped vias that can be filled with low resistance metals like aluminum, using high density plasma deposition to ensure homogeneous filling and regular via profiles, even in submicron spacings, thereby minimizing power dissipation and reducing the risk of device damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tungsten is used to fill vias in multilevel interconnect structures, then the structural strength and reliability are improved, but the electrical resistance increases leading to power dissipation issues
Solution Approach 1:
The patent changes the material parameter from tungsten to aluminum or copper, which have fundamentally different electrical conductivity properties. Aluminum and copper provide low electrical resistance while maintaining sufficient structural reliability for interconnect applications, directly resolving the contradiction between structural reliability and power dissipation.
2Loss of energy
If aluminum is used to fill vias, then the electrical resistance is reduced minimizing power dissipation, but the via profile regularity and filling homogeneity become difficult to achieve
Solution Approach 1:
The patent applies preliminary actions by first forming a liner layer on the via walls before filling with aluminum. The liner layer serves as a foundation that guides subsequent deposition processes and ensures uniform material distribution. Additionally, the via geometry is pre-optimized with specific aspect ratios and opening dimensions to facilitate homogeneous filling, preventing defects before they occur.
Solution Approach 2:
The patent changes the deposition parameters and via geometry parameters to optimize the filling process. By controlling via aspect ratio, opening size, and deposition conditions, the patent achieves regular via profiles and homogeneous aluminum filling, resolving the manufacturing precision challenge while maintaining low electrical resistance.
3Productivity
If the via spacing is reduced for miniaturization, then the functional density is increased, but the manufacturing precision and via profile control become more difficult
Solution Approach 1:
The patent changes critical parameters including via aspect ratio, opening dimensions, and spacing to enable miniaturization. By optimizing these parameters, the patent achieves smaller via dimensions with maintained profile regularity and filling homogeneity, allowing increased functional density while preserving manufacturing precision through carefully controlled geometric parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution allows for the creation of reliable multilevel interconnect structures with low resistance metal fillings, reducing power dissipation and enhancing the reliability of semiconductor devices by minimizing defects and irregularities in the via profiles, especially in high miniaturization and high-current applications.
Implementation Method 1
a layer of dielectric material deposited by means of high density plasma deposition
Data Source
AI summary
A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in connection with systems exhibiting submicron spacings. The architecture of the multilevel interconnect structure provides a low resistance connecting via.