Funneled Source/Drain Interface for Lower Nanosheet Parasitic Resistance
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Solution Overview
Problem
Conventional semiconductor devices face challenges in maintaining switching speeds and reducing current leakage as device dimensions shrink, leading to increased parasitic resistance between the source/drain region and the active nanolayer channel.
Innovation Solution
The introduction of a funneled interfacial region with a wide throat and a narrow throat in the source/drain region, formed by a funneling inner spacer, reduces parasitic resistance by increasing the junction thickness and optimizing the shape of the interfacial region between the source/drain region and the active nanolayer channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to follow Moore's law, then device density and operating speed are improved, but parasitic resistance between source/drain region and channel increases
Solution Approach 1:
The source/drain region is engineered with spatially varying properties: a first portion with higher doping concentration adjacent to the channel and a second portion with lower doping concentration extending outward. This local quality variation optimizes the electrical characteristics at the critical interface while managing parasitic resistance, allowing high carrier injection efficiency near the channel without excessive resistance in the extended region.
Solution Approach 2:
The source/drain region transitions from a conventional planar geometry to a three-dimensional structure that extends vertically and laterally. The region comprises multiple portions at different heights and positions relative to the channel, creating a multi-dimensional configuration that increases the effective contact area and reduces parasitic resistance while maintaining compact footprint.
2Area of stationary object
If source/drain region is made smaller to reduce device footprint, then device density is improved, but junction thickness decreases leading to increased parasitic resistance
Solution Approach 1:
The source/drain region utilizes vertical extension and lateral spreading to increase effective junction area without increasing the planar footprint. By configuring the region in three dimensions with portions at different heights and radial positions, the design achieves larger effective contact area within a compact footprint, thereby reducing parasitic resistance while maintaining high device density.
Solution Approach 2:
The source/drain region is configured with nested or overlapping portions where the first portion is positioned adjacent to the channel and the second portion extends outward, creating a nested spatial arrangement. This nesting allows the region to maximize its effective area within the constrained footprint by utilizing vertical and radial space efficiently.
Data Source
AI summary
A transistor includes a funneled interfacial source/drain (S/D) region that includes a narrow throat that is connected to or is an interface to the nanolayer channel. The funneled interfacial S/D region may also include a wide throat that is an interface to a remainder of the S/D region. The funneled interfacial source/drain (S/D) region may reduce parasitic resistance or impedance from the S/D region into or out of a nanolayer channel.