Furnace Insulation Cap Block Member for Oxidation Uniformity
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Solution Overview
Problem
Existing semiconductor fabrication methods for forming silicon oxide on silicon substrates face challenges in achieving uniform oxidation layer thickness, leading to variations that can affect the mechanical, electrical, and reliability properties of dies, and increase die failure rates.
Innovation Solution
A furnace system with an insulated housing, reaction chamber, wafer boat, block member, and truncated plates is used to control temperature uniformity, minimizing heat loss and directing process gas flow to enhance oxidation layer consistency across wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional thermal oxidation is used to form silicon oxide on silicon substrates, then the oxidation layer can be formed, but the thickness uniformity across wafers and on individual wafers is poor
Solution Approach 1:
The patent applies local quality by introducing dummy wafers at specific positions (top and bottom of the wafer stack) to create localized thermal zones that compensate for heat loss at the ends of the wafer boat. This ensures that all wafers, whether at the ends or in the middle of the stack, experience uniform heating conditions, thereby achieving consistent oxidation layer thickness across different spatial locations.
Solution Approach 2:
The patent changes the thermal parameters of the system by introducing dummy wafers that alter the heat distribution pattern within the reaction chamber. These dummy wafers modify the effective heating parameters for the actual wafers, ensuring that temperature variations across the wafer stack are minimized, which directly improves oxidation layer thickness uniformity.
2Productivity
If wafers are stacked vertically for batch processing, then productivity increases, but temperature uniformity across the wafer stack deteriorates due to heat loss at the ends
Solution Approach 1:
The patent addresses the temperature uniformity issue in vertical wafer stacking by applying local quality through dummy wafers positioned at the top and bottom of the stack. These dummy wafers create localized thermal compensation zones that prevent excessive heat loss at the ends of the wafer boat, ensuring that all wafers in the batch experience similar thermal conditions despite the vertical stacking configuration.
Solution Approach 2:
The dummy wafers act as thermal intermediaries between the heating source and the actual wafers at the ends of the stack. By introducing these intermediary elements, the system achieves more uniform heat distribution across the entire wafer stack, allowing batch processing to proceed with improved temperature uniformity while maintaining high productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves significant reduction in oxidation layer thickness variance, improving die integrity and reducing failure rates by maintaining precise temperature control and uniform gas distribution, resulting in consistent mechanical and electrical properties across all dies.
Implementation Method 1
a number of heating units arranged along the sidewall of the reaction chamber
Implementation Method 2
The block member covers the opening formed on the insulation cap, and thus the heat loss in the lower site of the reaction chamber is minimized
Implementation Method 3
the process gas is directed into the remote portion of the reaction chamber that is away from the gas exhaust, and thus the temperature in the remote portion is decreased
Implementation Method 4
The formation of silicon oxide on a silicon substrate is a frequently conducted process in the fabrication of semiconductor devices. One of the methods for forming silicon oxide is thermal oxidization which is carried out by subjecting a silicon wafer to an oxidizing ambient at elevated temperatures
Data Source
AI summary
A furnace for processing semiconductor wafers is provided. The furnace includes a tube having a closed upper end, an open lower end, and a sidewall connecting the upper end and the lower end. The furnace further includes a sealing lid removably connected to the lower end of the tube to define a reaction chamber. The furnace also includes an insulation cap connected to the sealing lid and positioned in the reaction chamber, and an opening is formed on a top surface of the insulation cap. In addition, the furnace includes a block member covering the opening and a wafer boat positioned on the top surface of the insulation cap.