Fuse Array Bank Layout for Faster Anti-Fuse Programming
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Solution Overview
Problem
The existing technology for replacing defective word lines and bit lines in semiconductor memory devices, such as DRAM, is time-consuming due to the lengthy operation required for writing in a fuse array.
Innovation Solution
A semiconductor memory device design that includes a controller chip and multiple memory chips stacked via through silicon via (TSV), utilizing anti-fuse units with parallel programming of anti-fuse arrays across multiple chips, allowing simultaneous selection and programming of anti-fuse units using identification codes and selection signals to reduce the overall programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fuse array is used to store defective line addresses, then the defective lines can be replaced with spare lines, but the programming operation takes a relatively long time
Solution Approach 1:
The fuse array is divided into multiple banks (first bank and second bank), allowing parallel programming operations to be performed on different segments simultaneously. This segmentation enables the system to maintain reliability while reducing total programming time by processing multiple address locations in parallel.
Solution Approach 2:
The patent introduces a bank dimension to the fuse array structure, transforming it from a single-dimensional array to a multi-dimensional structure with multiple banks. This dimensional expansion allows simultaneous access and programming of multiple fuse elements across different banks, thereby reducing programming time while maintaining the ability to store defective line addresses.
2Loss of information
If multiple fuse elements are programmed sequentially to store defective word line and bit line addresses, then complete address storage is achieved, but the overall programming time increases
Solution Approach 1:
The patent merges the programming operations of multiple fuse elements by enabling simultaneous programming across different banks. The control circuit coordinates parallel programming operations in the first and second banks, combining multiple programming tasks into a single coordinated operation that maintains address storage completeness while improving programming throughput.
Solution Approach 2:
The patent implements continuous useful action by allowing programming operations to proceed simultaneously in multiple banks without sequential waiting. The control circuit ensures that programming actions continue uninterrupted across different bank pairs, maximizing productivity while ensuring all necessary address information is stored.
Data Source
AI summary
An apparatus includes a memory chip including a plurality of fuse units, and a controller chip. Each fuse unit includes a fuse array having a plurality of fuse cells, a first register, and a second register. The controller is configured to set the fuse address in the second register included in selected one or more of the plurality of fuse units, set the match signal in the first register included in the selected one or more of the plurality of fuse units, and send a blow signal to the memory chip. Each of the selected one or more of the plurality of fuse units is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.