Fuse Array Broadcasting via N-bit Bus for Memory Redundancy

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Solution Overview

Problem

Current fuse array systems in memory devices are limited by their inflexibility and inefficiency in transmitting and programming fuse data, which hinders the ability to quickly and flexibly implement changes or tests without physically modifying the fuses, leading to increased die size and variability.

Innovation Solution

The implementation of an N-bit bus system for broadcasting fuse array data to local latches, allowing for faster and more flexible transmission and usage of fuse arrays, enabling the disposition of fuse latches anywhere on the die and facilitating test modes without physically altering the fuses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fuse array systems use traditional physical modification methods for programming and testing, then reliability is maintained, but device complexity and die size increase

Engineering Contradiction:
Improvefuse array system complexityVSAvoidfuse system reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent creates a virtual copy of the fuse array state through an N-bit bus system that can broadcast fuse data to local latches. This allows the system to simulate and test fuse configurations without physically modifying the actual fuses, thereby reducing device complexity while maintaining reliability through virtual modeling of fuse states.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces an N-bit bus as an intermediary between the fuse array and local latches. This bus system enables data transmission and broadcasting of fuse configurations without direct physical modification, serving as a mediator that reduces system complexity while preserving the reliability of the actual fuse elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If fuse array systems implement flexible data transmission methods, then productivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedata transmission speedVSAvoidfuse array programming precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the fuse array data into N-bit units that can be transmitted through the bus system to multiple local latches simultaneously. This segmentation enables parallel data transmission, improving productivity while the structured N-bit format maintains manufacturing precision by organizing fuse data into manageable, precise units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a temporal dimension to fuse array operations by enabling dynamic data broadcasting through the N-bit bus system. This allows fuse configurations to be transmitted and tested in time-critical applications without physical modification, improving productivity while the digital nature of the bus transmission maintains precision.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If fuse arrays are physically modified for testing and programming, then adaptability is improved, but loss of time increases

Engineering Contradiction:
Improvefuse array flexibilityVSAvoidprogramming and testing time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent enables preliminary testing and programming of fuse configurations through the N-bit bus system before physical implementation. The bus can broadcast test patterns and configurations to local latches, allowing the system to adapt and validate fuse arrangements in advance without time-consuming physical modifications.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates virtual representations of fuse configurations that can be rapidly copied and tested through the N-bit bus system. This allows multiple test scenarios to be evaluated quickly without physical modification, improving adaptability while significantly reducing the time required for programming and testing iterations.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS20190198127A1Systems and methods for improving fuse systems in memory devices
Publication Date: 2019.06.27 MICRON TECHNOLOGY INC
  • US20190198127A1 patent drawing
  • US20190198127A1 patent drawing
  • US20190198127A1 patent drawing

AI summary

A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.