Reservation Station Stalling for Fuse Array Load Replay Reduction

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Solution Overview

Problem

In out-of-order processors, the power wastage due to frequent load replays from non-core resources, such as fuse arrays and L2 caches, is significant, leading to increased power utilization and thermal issues, despite minimal performance impact.

Innovation Solution

Implementing a mechanism with reservation stations that detect specified load micro instructions and stall younger dependent micro instructions until the load from non-core resources is completed, reducing unnecessary replays and conserving power by managing execution unit power states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If load micro instructions are dispatched from reservation stations without stalling younger dependent instructions, then instruction throughput is improved, but power consumption increases due to frequent replays from non-core resources

Engineering Contradiction:

Improveinstruction throughputVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The mechanism performs preliminary detection of load micro instructions in the reservation station before dispatch. When a load to non-core resources is detected, the system proactively stalls younger dependent instructions in advance, preventing unnecessary replays and saving power before the replay condition occurs.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The invention introduces an intermediary mechanism between the reservation station and execution units that monitors load micro instructions and controls the dispatch of younger dependent instructions. This intermediary layer detects load operations to non-core resources and selectively stalls subsequent instructions, acting as a mediator that balances throughput and power consumption.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Use of energy by moving object

If younger dependent micro instructions are stalled until load from non-core resources is completed, then power consumption is reduced, but instruction execution latency increases

Engineering Contradiction:

Improvepower consumptionVSAvoidinstruction execution latency

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The stalling mechanism applies locally and selectively only to younger dependent instructions that are affected by loads to non-core resources, rather than globally stalling all instructions. This localized approach minimizes the impact on overall instruction execution latency while still achieving power savings by preventing replays.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system applies partial stalling action by selectively holding only the necessary younger dependent instructions in the reservation station until the load operation completes, rather than excessively stalling all instructions. This partial action reduces unnecessary latency while still preventing the harmful replay effect.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If execution units continuously operate to handle replayed instructions, then instruction completion is ensured, but thermal generation increases

Engineering Contradiction:

Improveinstruction completionVSAvoidthermal generation

Core Design Contradiction:

ReliabilityVSTemperature

Solution Approach 1:

The mechanism applies preliminary anti-action by preventing the replay condition from occurring in the first place. By detecting load micro instructions to non-core resources and stalling younger dependent instructions before they are dispatched, the system eliminates the cause of replays and their associated thermal generation, while still ensuring instruction completion through proper sequencing.

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS10089112B2Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor

Publication Date: 2018.10.02 VIA ALLIANCE SEMICON CO LTD

AI summary

An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a fuse array that stores configuration data.