Fuse Array Protrusion Design for Integrated Circuit
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Solution Overview
Problem
The robustness of fuse arrays in integrated circuits makes them difficult to break, as they undergo the same processing steps as metallization, leading to fuses being harder to break.
Innovation Solution
A fuse array design where a protrusion formed by the interlayer dielectric during chemical mechanical planarization reduces the height of the fuse channel, and additional dummy regions with a higher metal-to-dielectric ratio enhance material removal during CMP, making the fuse easier to break.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fuse array undergoes the same robust metallization processing steps, then the manufacturing reliability is improved, but the fuse becomes harder to break
Solution Approach 1:
The patent applies local quality by creating a protrusion structure in the interlayer dielectric material at the specific location where the fuse channel will be formed. This protrusion provides enhanced material removal during CMP processing only at the fuse channel location, while the rest of the metallization layers maintain their standard robust processing. The fuse channel region thus has a locally reduced height and enhanced material removal characteristics without compromising the overall manufacturing reliability of other circuit elements.
2Ease of operation
If the fuse channel height is reduced to make it easier to break, then the ease of operation is improved, but the manufacturing precision becomes more difficult to control
Solution Approach 1:
The patent applies preliminary action by forming the protrusion structure in the interlayer dielectric material before depositing the fuse channel metal layers. This protrusion is created during the CMP process that planarizes the interlayer dielectric, preparing the surface in advance for subsequent fuse channel formation. The protrusion pre-establishes the location and approximate height characteristics of the fuse channel region, making the subsequent metal deposition and patternning processes more controlled and predictable.
Solution Approach 2:
The patent applies parameter changes by utilizing the CMP process parameters to selectively remove interlayer dielectric material and create the protrusion structure. By controlling the CMP process conditions (such as slurry composition, pad pressure, and relative motion), the protrusion height and shape can be precisely controlled, thereby controlling the final fuse channel height and ensuring it falls within the desired range for easy breaking while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces the height of the fuse channel, making it easier to break at lower current/voltage and shorter times, while being compatible with existing back-end metallization processes.
Implementation Method 1
a protrusion formed by the interlayer dielectric during chemical mechanical planarization reduces the height of the fuse channel
Implementation Method 2
additional dummy regions with a higher metal-to-dielectric ratio enhance material removal during CMP
Data Source
AI summary
Embodiments of the present disclosure describe apparatuses, methods, and systems associated with a fuse array of an integrated circuit. An integrated circuit may include a first metallization layer including a plurality of trenches separated by an interlayer dielectric (ILD), wherein the ILD forms a protrusion that extends above a top surface of the trenches. An etch stop layer may be disposed on the first metallization layer. The integrated circuit may further include a fuse disposed on the etch stop layer, wherein the fuse includes a fuse channel coupled between an anode and a cathode, wherein the fuse channel is disposed directly above the protrusion and is in contact with the etch stop layer. The integrated circuit may additionally or alternatively include one or more dummy regions adjacent to the fuse channel and separated from the fuse channel by a dielectric material. Other embodiments may be described and/or claimed.