Fuse Array Layout With Shared Wiring for Redundant Memory Repair
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Solution Overview
Problem
The increasing number of redundant structures in memory devices to improve yield consumes more area and increases power consumption, reducing efficiency.
Innovation Solution
The implementation of an improved fuse array with reduced footprint, utilizing shared wiring and parallel configurations of fuse circuits to reduce the number of gates and area consumption, and sharing fuse circuits between redundant memory addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of redundant structures (fuse arrays) is increased to improve yield and redundancy, then the reliability of the memory device is improved, but the area consumed and power consumption increase
Solution Approach 1:
The patent merges the fuse latch circuit and matching circuit into a single integrated fuse circuit unit. The fuse latch stores address bits and the matching circuit compares these stored bits with incoming address bits, combining functions that were previously separate into one compact structure. This reduces the total area required for redundant structures while maintaining the same reliability functionality.
Solution Approach 2:
The fuse circuit is designed with multi-functionality, where the same circuit structure serves both as a storage element (fuse latch) and a comparison element (matching circuit). This universal design allows the circuit to perform multiple functions within a smaller footprint, reducing the area required for each redundant structure instance.
2Reliability
If the number of redundant structures (fuse arrays) is increased to improve yield and redundancy, then the reliability of the memory device is improved, but the power consumption increases
Solution Approach 1:
By combining the fuse latch and matching circuit into one integrated unit, the patent reduces the total number of separate circuit components required. This merger reduces static power consumption associated with multiple separate circuits while maintaining the same redundancy capability. The integrated design eliminates redundant power consumption from separate latch and matching circuit operations.
3Reliability
If the number of redundant structures is increased to improve yield, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The integration of fuse latch and matching circuit into a single fuse circuit unit reduces device complexity by eliminating the need for separate interconnected circuits. The merged structure simplifies the overall device architecture while maintaining full redundancy functionality, making the device less complex despite increased redundancy capabilities.
4Area of stationary object
If the footprint of fuse circuit is reduced by sharing wiring and using parallel configurations, then the area consumed is reduced, but the device complexity may increase
Solution Approach 1:
The fuse circuit is segmented into parallel functional blocks (fuse latch and matching circuit) that operate independently but are integrated within the same structure. This segmentation allows for compact wiring and reduced area while maintaining clear functional separation, preventing excessive complexity despite the integrated design.
Data Source
AI summary
A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.