Fuse Box Memory Repair for Wireless Devices
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Solution Overview
Problem
There is a need for an efficient method and apparatus to repair memory defects in wireless communication devices using a multi-way fuse box-based approach, as existing methods are time-consuming and costly, and primarily focus on single bit failures in sub-20 nm range processors.
Innovation Solution
A method and apparatus that involves testing memories using a production test pattern, determining failing memories, and using a fuse register pattern to blow fuses in redundant memories for repair, with a fuse programmable read-only memory (FPROM) and a fuse box memory repair (FMR) apparatus to facilitate independent memory repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory testing and repair methods are used, then memory defects can be repaired, but the process is time-consuming and expensive
Solution Approach 1:
The patent implements built-in self-test (BIST) controllers and repair analysis programs that are pre-integrated into the SoC memory system. These preliminary actions enable automatic detection and repair of memory defects during manufacturing without requiring external testing equipment, thereby reducing test time while maintaining repair capability
Solution Approach 2:
The memory system performs self-diagnosis and self-repair through integrated BIST controllers and repair logic. The system automatically identifies failing memory locations and activates redundant rows or columns through fuse blowing without external intervention, eliminating the need for time-consuming external testing and repair processes
2Measurement precision
If comprehensive memory testing is performed, then all memory defects are detected, but the testing process becomes expensive and time-consuming
Solution Approach 1:
The patent employs built-in self-test controllers that are integrated into the memory system itself. These controllers automatically execute test patterns and detect defects without requiring external testing equipment, thereby maintaining high defect detection accuracy while significantly improving testing efficiency and reducing costs
Solution Approach 2:
The BIST controllers serve multiple functions: they perform comprehensive memory testing, analyze test results to identify failing locations, and coordinate repair operations. This multi-functionality eliminates the need for separate testing and repair equipment, improving productivity while maintaining measurement precision
3Reliability
If multiple memories are repaired using traditional fuse methods, then each memory can be repaired, but the number of fuses required increases
Solution Approach 1:
The patent implements a shared fuse box that is common to multiple memory blocks within the SoC. Instead of having separate fuse boxes for each memory, the fuse box is merged into a shared resource that can repair multiple memories, thereby reducing the total number of fuses required while maintaining comprehensive repair coverage
Solution Approach 2:
The fuse box is designed as a universal repair mechanism that can service multiple different memory blocks. The repair logic and fuse allocation are managed centrally, allowing a single fuse box to provide repair capability across multiple memories, thus reducing device complexity and fuse quantity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces test time and costs by enabling efficient repair of multiple memories with a limited number of fuses, improving production yields and ensuring design verification, while providing faster memory repair with reduced disruption.
Implementation Method 1
Repairs may be accomplished using redundant rows and columns built into the memory. These redundant elements are enabled by blowing a fuse
Data Source
AI summary
A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.