Fuse Cell Circuit With Shared Active Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing fuse cell arrays face challenges in reducing area consumption while maintaining reliability, particularly due to the need for large transistors and amplifiers for data sensing in e-fuse technology, which limits their effectiveness in programming and reading operations.
Innovation Solution
A fuse cell circuit design that includes a bit line, first and second fuse transistors with select transistors, where the transistors share active regions and gate oxide layers, eliminating the need for isolation layers and allowing for reduced area consumption and improved reliability by using shared active regions and uniform process design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of the transistor is increased to directly recognize data without a separate sensing operation, then the data sensing capability is improved, but the area of the e-fuse increases
Solution Approach 1:
The patent merges the fuse transistor with the sense transistor by sharing the active region and gate oxide layer. The fuse transistor's channel region is formed in the same active region as the sense transistor, eliminating the need for separate isolation structures. This merging allows data sensing without requiring a larger dedicated sensing transistor, thus improving measurement precision while maintaining compact area.
2Area of stationary object
If an amplifier is used to sense the current flowing in the transistor without increasing the size of the transistor, then the transistor size is reduced, but the device complexity increases
Solution Approach 1:
The patent combines the fuse transistor and sense transistor into a single integrated structure sharing common active regions and gate oxide layers. This merging eliminates the need for external amplifiers by enabling direct current sensing through the shared channel, thus reducing device complexity while maintaining compact transistor size.
3Reliability
If isolation layers are used to separate fuse transistors, then the reliability is improved, but the area consumption increases
Solution Approach 1:
The patent merges adjacent fuse transistors by forming their channel regions in shared active regions without intervening isolation layers. The gate oxide layers are formed continuously over the semiconductor substrate between active regions, providing electrical isolation through the oxide itself rather than requiring separate isolation structures. This approach maintains reliability through proper electrical isolation while significantly reducing area consumption.
4Loss of information
If the gate oxide layer is destroyed to program the e-fuse, then the data storage capability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by destroying the gate oxide layer only in specific regions corresponding to selected fuse transistors while maintaining intact gate oxide layers in other regions. This is achieved by selectively applying high voltage to specific word lines during programming, causing localized oxide breakdown only where needed. The shared gate oxide structure allows precise local modification without affecting adjacent fuse elements, thus improving data storage capability while managing manufacturing precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design reduces the area required for fuse cell arrays, enhances reliability, and allows for efficient programming and reading operations without the need for additional amplifiers, thereby improving the overall performance of the memory device.
Implementation Method 1
when a high power supply voltage, which the transistor T cannot withstand, is applied to the gate G, the gate G and the drain/source D/S may short-circuit as the gate oxide of the transistor T is destroyed
Data Source
AI summary
A fuse cell circuit may include a bit line, a first fuse transistor having first and second program states, a first select transistor coupled between one terminal of the first fuse transistor and the bit line, and suitable for turning on when the first fuse transistor is selected, a second fuse transistor including one terminal coupled to the other terminal of the first fuse transistor, and having first and second program states, and a second select transistor coupled between a other terminal of the second fuse transistor and the bit line, and suitable for turning on when the second fuse transistor is selected.