Fuse Circuit Layout With Deep Trench Isolation for Compact Memory Repair
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Solution Overview
Problem
The increasing number of data bits handled by fuse circuits in semiconductor devices leads to an expansion of the occupied area, necessitating miniaturization and preventing malfunctions caused by short-circuits and parasitic transistor activation.
Innovation Solution
The semiconductor device incorporates a plurality of fuse circuits with fuse elements and cutting transistors arranged in a specific configuration, where each fuse element is surrounded by deep trench isolation, and cutting transistors are formed in a well region with power supply parts surrounded by deep trench isolation, reducing parasitic resistance and preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of data bits handled by fuse circuits is increased, then the functionality of the semiconductor device is improved, but the occupied area of the fuse circuit region increases
Solution Approach 1:
Multiple power supply parts for different cutting transistors are merged into a single common power supply part, eliminating redundant power supply structures and reducing the overall occupied area while maintaining functionality for handling multiple data bits
Solution Approach 2:
The common power supply part serves multiple cutting transistors simultaneously, providing universal power supply functionality to all fuse circuits in the array, which reduces the area required compared to having dedicated power supply parts for each transistor
2Reliability
If deep trench isolation parts are provided around each fuse element and power supply parts, then short-circuits between adjacent elements are prevented, but the occupied area increases
Solution Approach 1:
Adjacent deep trench isolation parts are merged into a continuous common deep trench isolation structure that surrounds multiple power supply parts and cutting transistors, maintaining short-circuit prevention functionality while reducing the total area occupied by isolation structures
Solution Approach 2:
The fuse circuit region is segmented into distinct functional areas (fuse element region, cutting transistor region, power supply region) separated by deep trench isolation parts, which prevents short-circuits while allowing compact arrangement of each segment
3Reliability
If cutting transistors are formed in a well region with power supply parts, then parasitic resistance is reduced and malfunction is prevented, but the device complexity increases
Solution Approach 1:
Multiple power supply parts are merged into a single common power supply part that serves all cutting transistors, reducing the number of discrete components and simplifying the overall device structure while maintaining low parasitic resistance through the common well region connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for the miniaturization of semiconductor devices by reducing the occupied area of the fuse circuit region while preventing malfunctions due to short-circuits and parasitic transistor activation.
Implementation Method 1
each of the plurality of fuse elements is surrounded by respective first deep trench isolation parts. In plan view, each of the plurality of cutting transistors is surrounded by respective power supply parts, and the plurality of power supply parts are integrally surrounded by a second deep trench isolation part
Implementation Method 2
The plurality of cutting transistors are formed in a well region, and each of the plurality of power supply parts has the same conductivity type as the well region and is formed in the well region
Data Source
AI summary
A semiconductor device includes fuse circuits, and each of the fuse circuits includes fuse elements and cutting transistors. The fuse elements and the cutting transistors are arranged in a first direction of a first main surface of a semiconductor substrate, respectively, and each of the fuse elements is surrounded by each of deep trench isolation parts in plan view. In plan view, each of the cutting transistors is surrounded by each of power supply parts, and the power supply parts are integrally surrounded by the deep trench isolation part. The cutting transistors are formed in a well region, and each of the power supply parts has the same conductivity type as the well region and is formed in the well region.