Fuse Circuit Offset Voltage Adjustment in Semiconductor Devices
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Solution Overview
Problem
In semiconductor devices, accurately adjusting offset voltage in miniaturized ICs with limited space is challenging due to element variations, and existing methods require additional test nodes or suffer from inconsistent current drive forces, leading to inaccuracies and increased test time.
Innovation Solution
A semiconductor device with a fuse section that generates switch control signals, allowing for adjustment of offset voltage in a differential amplifier without cutting fuses, by simulating fuse cut states using switch control signals and constant current sources, enabling precise adjustment of offset voltage before actual cutting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a test node is added to realize the internal circuit state after fuse cutting, then the adjustment value can be confirmed before fuse cutting, but the circuit area increases
Solution Approach 1:
The fuse cutting node is made multi-functional by enabling it to serve both its original purpose (fuse cutting) and the new function of confirming adjustment values. By applying a specific voltage to the fuse cutting node, the circuit simulates the post-cut state without requiring additional test nodes, thus achieving measurement confirmation while avoiding extra circuit area.
Solution Approach 2:
Instead of adding a physical test node to measure the adjustment value, the invention creates a virtual copy of the post-cut circuit state by applying voltage to the fuse cutting node. This virtual copying allows the adjustment value to be confirmed in a simulated environment that mirrors the actual post-cut conditions without physical duplication of circuit elements.
2Measurement precision
If element variations are considered to achieve high accuracy adjustment, then the desired adjustment value cannot be obtained even with correct fuse cutting, but adding adjustment elements increases circuit complexity
Solution Approach 1:
The invention performs preliminary verification of the adjustment value by simulating the fuse-cut circuit state before actual fuse cutting. By applying voltage to the fuse cutting node and measuring the adjustment value in advance, the system can predict whether the desired offset voltage adjustment will be achieved, allowing for re-adjustment if necessary before committing to the fuse cutting operation.
Solution Approach 2:
The system implements a feedback mechanism where the adjustment value is measured and confirmed in the simulated post-cut state, and this information is used to determine whether the actual fuse cutting should proceed. If the measured adjustment value does not meet the desired specifications, the process can be adjusted before fuse cutting, ensuring high accuracy while avoiding unnecessary circuit complexity.
3Manufacturing precision
If fuse cutting is performed based on design values without considering element variations, then the adjustment may be inaccurate, but measuring each element increases test time
Solution Approach 1:
The fuse cutting node serves itself by performing dual functions: it is both the node where fuse cutting occurs and the node where adjustment value confirmation is performed. By utilizing the existing fuse cutting node for both purposes, the system avoids adding separate measurement infrastructure that would increase test time, while still achieving accurate adjustment verification through voltage application and measurement at the same node.
Data Source
AI summary
A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage.