Fuse Circuit Parity Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuits with conventional fuse circuits face errors due to faulty gate dielectric layers, leading to incorrect fuse signal generation, which can cause operational errors.
Innovation Solution
A fuse circuit design that includes a programming fuse signal generation block, a corrected pulse generation block, and a fuse unit, which uses parity signals and error correction mechanisms to reprogram fuse signals and prevent operational errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional fuse circuit is used to program internal settings, then the circuit can be configured without changing design, but errors occur when programming due to faulty gate dielectric layers
Solution Approach 1:
The patent applies preliminary action by generating parity signals before fuse programming and storing them in parity holding circuits. This pre-computed error detection data is held ready to correct programming errors that occur during fuse operation, allowing the system to proactively prevent errors rather than reactively handle them
Solution Approach 2:
The patent implements feedback through XOR circuits that continuously compare current fuse signals with stored parity signals. When a discrepancy is detected (indicating a programming error), the system uses the parity feedback to generate corrected fuse signals, creating a closed-loop error correction mechanism
2Manufacturing precision
If electrical stress is applied to program fuses, then the electrical connection state changes from open to short or vice versa, but gate dielectric layer failures cause erroneous signal generation
Solution Approach 1:
The patent changes the parameter verification approach by introducing parity bits that encode the expected state of fuse signals. Instead of relying solely on the physical integrity of the gate dielectric layer, the system uses logical parameter verification through XOR comparisons to detect and correct programming errors
Solution Approach 2:
The patent introduces parity holding circuits and XOR circuits as intermediary components between the fuse signals and the final output. These intermediaries act as mediators that detect discrepancies caused by gate dielectric failures and provide corrected signals, isolating the fault from the functional output
3Reliability
If parity signals are generated and held for error correction, then programming errors can be corrected, but the circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the error correction function into separate parity holding circuits for each fuse signal group. This modular approach allows error correction to be implemented incrementally and maintains organization, making the increased complexity more manageable and potentially allowing selective application to critical fuse groups
Data Source
AI summary
A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.