Electric Fuse Circuit with Shared IO Transistor for Area Reduction
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Solution Overview
Problem
Conventional electric fuse circuits require large-area transistors and dedicated testers for programming, leading to increased manufacturing costs and chip area, especially when used in high-density semiconductor applications like system LSI chips, due to the need for high currents and numerous control terminals.
Innovation Solution
The electric fuse circuit design incorporates a first and second switch transistor in series with the fuse element, allowing current passage only when both are on, using a low-breakdown voltage logic transistor as the first switch and a thicker-gate-oxide IO transistor as the second, shared across multiple fuse cores, with a level shift circuit for voltage conversion during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a single thick-gate-oxide transistor is used to feed current to fuse the element, then the transistor area increases, but using a smaller logic transistor with thinner gate oxide causes TDDB degradation
Solution Approach 1:
The current feeding function is divided between two transistors: a small logic transistor (first transistor) for control and a larger IO transistor (second transistor) for current delivery. This segmentation allows each transistor to be optimized for its specific function, preventing the need for a single large transistor while avoiding TDDB degradation in the control transistor.
Solution Approach 2:
The IO transistor acts as an intermediary between the power source and the fuse element, handling the high current and voltage stress that would otherwise degrade the logic transistor. This mediator protects the logic transistor from harmful electrical stress while enabling efficient fuse programming.
2Productivity
If high current is applied to fuse multiple fuse elements simultaneously, then programming speed increases, but existing general-purpose testers cannot concentrate the required current
Solution Approach 1:
The circuit dynamically controls current distribution by sequentially activating individual fuse elements through the program enable signal. This allows the use of standard testers with lower current capability, as only one fuse element is programmed at a time, while maintaining overall programming efficiency through automated sequential operation.
Solution Approach 2:
The programming process uses periodic clock signals to sequentially enable different fuse elements at different time periods. This time-division multiplexing approach allows standard testers to program multiple fuse elements by rapidly switching between them, achieving effective multi-element programming capability with single-element current limits.
3Quantity of substance
If many independent electric fuse circuits are mounted in a system LSI for redundancy relief, then the number of controlled fuse elements increases, but the number of control terminals becomes unmanageable
Solution Approach 1:
Multiple fuse element control functions are merged into a single shared IO transistor that is controlled by a single program enable terminal. This consolidation reduces the control terminal count from one per fuse element to one shared terminal, dramatically simplifying the interface while maintaining the ability to control many fuse elements through sequential activation.
Solution Approach 2:
The shared IO transistor and program enable terminal serve multiple fuse elements universally, rather than being dedicated to a single fuse element. This multi-functional design allows the same control infrastructure to manage a large array of fuse elements, reducing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the circuit area, delays transistor degradation, and allows for more efficient programming using existing general-purpose testers, making the OTP memory more cost-effective and suitable for high-density applications.
Implementation Method 1
an instantaneous carrying current required to fuse the silicide layer is 10 to 30 mA (milliamperes) for a 130- or 90-nm process generation
Data Source
AI summary
A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.