Semiconductor Fuse Circuit Tunnel Layer Surrounding Charge Trap
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Solution Overview
Problem
In flash memory devices, fuses deteriorate electrical properties due to electron leakage from the charge trap layer through the tunnel layer, leading to poor electrical connections between adjacent semiconductor circuits.
Innovation Solution
A semiconductor fuse circuit design where a tunnel layer is configured to surround a charge trap layer, preventing electron de-trapping and enhancing the transistor characteristics of fuses, thereby maintaining stable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuses are used to electrically connect adjacent semiconductor circuits using the charge trap layer, then electrical connection between circuits is achieved, but electron leakage through the tunnel layer causes de-trapping and deteriorates electrical properties
Solution Approach 1:
The charge trap layer is divided into multiple segments along the channel length, with each segment independently controllable. This segmentation allows specific trap regions to be activated or deactivated, preventing electron leakage while maintaining electrical connection functionality. The tunnel layer is also segmented to correspond with charge trap segments, creating isolated regions that prevent harmful electron migration.
Solution Approach 2:
Different regions of the charge trap layer are assigned different functional qualities - some regions are optimized for electron trapping to enable electrical connection, while other regions are designed with enhanced barrier properties to prevent electron leakage. The tunnel layer thickness and material composition are locally adjusted to match the functional requirements of each charge trap region.
2Manufacturing precision
If the tunnel layer is made thinner to improve charge trapping efficiency, then transistor characteristic is enhanced, but electron leakage increases and electrical properties deteriorate
Solution Approach 1:
The structure employs nested layers where the charge trap layer is positioned within and surrounded by the tunnel layer. This nesting arrangement allows the charge trap layer to be thin enough for efficient electron trapping while the outer tunnel layer provides a protective barrier that prevents electron leakage to the substrate, resolving the contradiction between trapping efficiency and leakage prevention.
Solution Approach 2:
The patent uses composite material structures combining different dielectric materials with complementary properties - one material optimized for electron trapping affinity and another for barrier properties. This composite approach enables the tunnel layer to simultaneously achieve thin thickness for trapping efficiency while maintaining high barrier properties to prevent leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents electron leakage, improving the electrical properties of flash memory devices and semiconductor modules by ensuring reliable electrical connections and data storage.
Implementation Method 1
a tunnel layer is configured to surround a charge trap layer in a semiconductor substrate
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate.