Fuse Driver Circuit Robustness Against ESD and EOS
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Solution Overview
Problem
Polysilicon fuses in semiconductor devices are vulnerable to damage from electrostatic discharge (ESD) and electrical overstress (EOS) events, which can cause them to malfunction or become useless due to high currents, undervoltage, and overvoltage conditions.
Innovation Solution
The implementation of a fuse driver circuit comprising a NMOS and PMOS transistor configuration, where the drain of the NMOS transistor is connected to the negative end of the fuse and the source to ground, and the drain of the PMOS transistor is connected to the positive end of the fuse, providing enhanced robustness by controlling current flow through the use of pull-down and pull-up transistors to protect against undervoltage and overvoltage events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fuse driver circuit uses a simple configuration without pull-up and pull-down transistors, then the device complexity is reduced, but the reliability of the fuse under undervoltage and overvoltage conditions deteriorates
Solution Approach 1:
The patent introduces pull-up and pull-down transistors as intermediary components between the fuse and the power supply/ground. These transistors act as mediators that control current flow to the fuse, protecting it from harmful voltage conditions while allowing normal operation. The pull-up transistor (PMOS) prevents overvoltage damage by controlling current from VDD, and the pull-down transistor (NMOS) prevents undervoltage damage by controlling current to ground.
2Productivity
If the fuse is exposed to high currents during ESD or EOS events, then the intended fuse blowing function can be achieved, but the fuse may be rendered useless due to excessive current damage
Solution Approach 1:
The patent implements protective cushioning by placing pull-up and pull-down transistors in series with the fuse before harmful ESD or EOS events can directly affect it. These transistors are designed to fail safely in a controlled manner, absorbing or limiting the harmful current surge before it reaches the fuse, thereby cushioning the fuse from destructive current levels while still allowing the fuse to perform its intended protection function.
Data Source
AI summary
Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.