Fuse Error Detection Circuit for Stable Memory Redirection
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Solution Overview
Problem
Existing semiconductor memory devices face reliability issues due to inaccurate reading of fuse states, which can lead to healthy memory cells being replaced by defective ones, affecting data integrity and performance.
Innovation Solution
A fuse error detection circuit generates signature data for consecutive fuse read operations and compares it to detect errors, providing a match signal to indicate discrepancies, thereby enabling verification of fuse data stability and preventing operation when errors are detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuse read operations are performed to redirect addresses of defective memory cells, then memory reliability is improved, but errors in reading fuse states may cause healthy memory cells to be replaced by defective ones, worsening data integrity
Solution Approach 1:
The patent implements a feedback mechanism by comparing fuse data from multiple read operations. The fuse read circuit performs sequential reads and compares the results to detect inconsistencies. When differences are detected between read operations, the system identifies potential reading errors and can request re-reading or trigger error handling, thereby improving measurement precision through iterative verification.
Solution Approach 2:
The patent performs preliminary fuse data verification before using the fuse information for memory cell redirection. By conducting multiple read operations and comparisons in advance, the system ensures that only accurate fuse data is used for addressing, preventing healthy cells from being incorrectly marked as defective before the actual memory operation begins.
2Measurement precision
If complete fuse data sets are compared to detect errors, then measurement precision is improved, but device complexity and physical space requirements increase
Solution Approach 1:
The patent extracts only the essential comparison function from the full fuse data verification process. Instead of comparing all fuse data bits simultaneously, the circuit selectively compares critical portions of the fuse data that are most indicative of reading errors. This extraction approach maintains adequate measurement precision while significantly reducing circuit complexity and physical space requirements.
Solution Approach 2:
The patent implements partial verification by performing comparisons on a subset of fuse data rather than the complete data set. The system reads and compares fuse data in segments or focuses on specific critical bits, achieving sufficient error detection capability with reduced computational and physical resources compared to exhaustive full-data comparison.
Data Source
AI summary
An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.