Fuse-Fetching Circuit Using Shift Register for Chip Area Reduction

The patent combines the latch function and delay function into a single integrated circuit block that works cooperatively with the fuse array. Instead of replicating separate latch and delay elements for each fuse, the invention merges these functions into shared resources that serve multiple fuses, thereby reducing overall hardware complexity while maintaining reliable information storage and control.

The latch circuit and delay element are designed as universal components that can serve multiple fuse units. The latch can hold information from different fuses at different times, and the delay element provides timing control for multiple operations. This multi-functionality eliminates the need for dedicated latch and delay elements for each individual fuse, reducing hardware cost while ensuring reliable operation.

The invention segments the fuse array into multiple rows and columns, with fuses arranged in a grid pattern. Instead of replicating complete fuse units (each with latch and delay elements), the segmentation allows shared latch and delay resources to serve multiple segmented fuse groups. This segmented organization maintains comprehensive fuse-fetch capability while dramatically reducing the area required by eliminating redundant components in each replication.

Multiple fuse units share common latch circuits and delay elements. The latch and delay functions are merged into shared resources that can be time-multiplexed across different fuse units. This merging approach enables the system to handle multiple fuses without requiring proportional increases in hardware, thus completing fuse-fetch tasks efficiently while minimizing chip area consumption.

The latch circuit is designed as a universal storage element that can hold information from any fuse unit. Instead of dedicating a separate latch to each fuse, the universal latch can be selectively activated to store information from different fuses at different times. This multi-functional approach ensures reliable information storage while avoiding the hardware cost and layout area increase that would result from replicating latches for each fuse unit.

The invention introduces control signals and timing mechanisms that act as intermediaries between the fuse units and the shared latch. These intermediary control elements manage the timing and selection of which fuse information is loaded into the latch, ensuring reliable storage without requiring additional latch elements. The intermediary control logic coordinates the shared resources to serve multiple fuses effectively, maintaining storage reliability while minimizing hardware complexity.