Electrical Fuse Formation in Multiple Patterning Interconnects

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current interconnect structures and fabrication methods for back-end-of-line (BEOL) interconnects in semiconductor devices face challenges in achieving improved connectivity and efficiency, particularly in forming discrete interconnects with varying widths and programming electrical fuses for dynamic circuit modifications.

Innovation Solution

The method involves forming mandrel lines with selective cuts and sidewall spacers to create trenches in an interlayer dielectric layer, where the conductor widths of interconnects and fuse links are tailored to achieve specific dimensions, allowing for efficient connection and programming of electrical fuses within a single metallization level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional multiple patterning processes are used to form interconnect structures, then standard interconnect formation is achieved, but the ability to form interconnects with varying widths and program electrical fuses is limited

Engineering Contradiction:
Improveability to form interconnects with varying widthsVSAvoidfabrication process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the mandrel line into multiple sections by forming cuts at specific locations. Each mandrel section generates sidewall spacers that define different interconnect widths. The first mandrel section forms a first-width interconnect, while the second mandrel section forms a second-width interconnect, enabling varied interconnect widths from a single mandrel structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by forming mandrel cuts and sidewall spacers before the final interconnect formation. The mandrel sections are prepared in advance with predetermined cut locations, and sidewall spacers are formed on these sections to pre-establish the width variations before trench etching and conductor deposition.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If electrical fuses are to be programmed dynamically, then circuit adaptability is improved, but additional fabrication steps and process complexity increase

Engineering Contradiction:
Improvedynamic circuit programming capabilityVSAvoidfabrication efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the formation of varied-width interconnects and electrical fuses into a single integrated process flow. Both structures are formed simultaneously using the same mandrel-based multiple patterning technique, trench etching, and conductor deposition steps, eliminating the need for separate fabrication processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal fabrication approach where the mandrel-cut-sidewall spacer technique serves multiple functions: it defines both standard interconnects and electrical fuses, and it produces both uniform-width and varied-width interconnect structures using the same fundamental process steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11348870B2Electrical fuse formation during a multiple patterning process
Publication Date: 2022.05.31 GLOBALFOUNDRIES US INC
  • US11348870B2 patent drawing
  • US11348870B2 patent drawing
  • US11348870B2 patent drawing

AI summary

Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.