Fuse Isolation Circuit for Leakage Control in Memory ICs
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Solution Overview
Problem
Semiconductor memory devices experience unnecessary leakage current due to remnants of cut fuses, which deteriorate power performance by creating a current path with high resistance.
Innovation Solution
The implementation of a cut-off unit circuit that electrically isolates the fuse from the input to the status information circuit after latching the fuse status, using a holding and outputting circuit with cross-coupled inverters to prevent leakage current by disconnecting the fuse from the supply voltage during initialization and reconnecting it after status information is latched.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fuse is cut to repair defective memory cells, then the defective cells can be replaced with redundancy cells, but fuse remnants remain and create a high resistance current path causing leakage current
Solution Approach 1:
The fuse circuit is divided into separate functional blocks: the fuse cutting section, the status information generation section, and the holding/output section. This segmentation allows the fuse to be cut for defect repair while isolating the remnants from creating leakage current paths through proper circuit design with transistors that control current flow paths.
Solution Approach 2:
Transistors (such as NMOS transistors) are introduced as intermediary components between the fuse and the rest of the circuit. These transistors act as switches that can open or close current paths, allowing the fuse status to be detected while preventing fuse remnants from creating unwanted leakage current paths to ground or power supply.
2Ease of operation
If the constant voltage signal is gradually increased from low level to high level, then the circuit can properly initialize and output status information, but during this transition period both PMOS and NMOS transistors may be turned on creating a current path
Solution Approach 1:
The circuit is designed with transistors configured such that during the voltage transition period, the current path through both PMOS and NMOS transistors is prevented from being simultaneously active. The holding and outputting unit is prepared in advance to latch the status information once the voltage reaches the high level, avoiding the need for both transistors to be on during transition.
Solution Approach 2:
The circuit utilizes dynamic transistor switching based on the constant voltage signal level. The transistors are designed to change their conduction states dynamically as the voltage transitions, ensuring that at no point during the transition are both PMOS and NMOS transistors fully conductive, thereby preventing the creation of a low-impedance current path.
Data Source
AI summary
A fuse circuit can include a cut-off unit circuit configured to electrically isolate a fuse from an input to a status information circuit after latching of status information associated with status of the fuse. Other fuse related circuits and methods are disclosed.