Fuse Latch Error Correction Mechanism for Soft Error Mitigation
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Solution Overview
Problem
The reduction in size of semiconductor memory devices leads to increased soft error rates due to insufficient drive capacity and external influences, causing data corruption in fuse latches used for storing configuration information.
Innovation Solution
Incorporating error correction circuits that generate and apply error detection/correction data in real-time to the fuse latches, shared across multiple latches, to detect and correct data corruption, thereby reducing soft errors and maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the physical size of the memory device is reduced, then the device footprint is decreased, but the soft error rate increases due to insufficient drive capacity
Solution Approach 1:
The patent divides the error correction function into segments by implementing separate first and second error correction codes for different portions of latched data. This segmentation allows targeted protection of critical data paths while maintaining overall system reliability despite reduced device size
Solution Approach 2:
The patent applies preliminary action by pre-charging capacitive nodes to specific voltage levels before data operations. This preliminary voltage establishment ensures sufficient drive capacity and noise margins are maintained even in scaled-down devices, preventing soft errors before they can occur
2Area of moving object
If the latch size is reduced to decrease footprint, then the drive capacity for loading and accessing information is reduced, but this leads to increased data errors
Solution Approach 1:
The patent applies local quality by implementing different error correction strategies for different data paths. First error correction code is applied to first latched data while second error correction code is applied to second latched data, allowing each latch to be optimized for its specific function and error profile
Solution Approach 2:
The patent implements feedback mechanisms where error correction codes are continuously monitored and applied to correct errors in latched data. This feedback loop ensures that even with reduced latch size and drive capacity, data integrity is maintained through active error detection and correction
3Reliability
If error correction circuits are added to reduce soft errors, then data integrity is improved, but device complexity increases
Solution Approach 1:
The patent achieves universality by implementing error correction circuits that serve multiple functions: they correct soft errors in latched data, provide data integrity verification, and maintain compatibility with existing memory architectures. This multi-functionality justifies the added complexity by delivering comprehensive protection across different data paths
Data Source
AI summary
Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.