Fuse Latch N-P-P-N-N Active Region Arrangement
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently arranging fuse-related circuits to enhance regional integration and resistance to soft errors, particularly due to instability caused by ionizing radiation, which leads to data malfunctions known as soft errors.
Innovation Solution
A fuse latch design incorporating specific arrangements of NMOS and PMOS transistors in active regions, including data transmission, latch, and output circuits, which increases resistance to soft errors and improves regional integration by isolating transistor terminals and arranging active regions in an N-P-P-N-N structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fuse-related circuits are arranged to increase regional integration, then device complexity is reduced, but resistance to soft errors deteriorates due to ionizing radiation instability
Solution Approach 1:
The fuse latch circuit is segmented into distinct active regions (first through fifth active regions) that are spatially separated and organized in an N-P-P-N-N structure. This segmentation isolates different functional blocks (data transmission, latch, output) into separate regions, reducing interference from ionizing radiation while maintaining high regional integration.
Solution Approach 2:
The patent introduces intermediate structures between transistor terminals, including isolation regions and specific wiring arrangements that act as mediators to protect against soft errors. These intermediary elements buffer the effect of ionizing radiation on critical data storage nodes while maintaining circuit functionality.
2Reliability
If transistor terminals are isolated to increase resistance to soft errors, then reliability is improved, but device area increases
Solution Approach 1:
The patent merges multiple functional circuits (data transmission circuit, latch circuit, output circuit) into a single integrated fuse latch structure with shared power supply and ground connections. This merging reduces the overall device area while maintaining the isolation benefits through the N-P-P-N-N active region arrangement.
Solution Approach 2:
The isolation of transistor terminals is achieved not only through spatial separation in the planar dimension but also through vertical stacking and three-dimensional wiring arrangements. This dimensional approach allows isolation without proportionally increasing the footprint area.
3Reliability
If active regions are arranged in N-P-P-N-N structure to reduce soft error impact, then resistance to soft errors is improved, but manufacturing complexity increases
Solution Approach 1:
The N-P-P-N-N active region arrangement utilizes standard semiconductor manufacturing parameters and existing process capabilities. The structure leverages conventional photolithography and doping techniques to create the alternating N-type and P-type regions, avoiding the need for exotic or overly complex manufacturing processes.
Data Source
AI summary
A fuse latch of a semiconductor device including PMOS transistors and NMOS transistors includes a data transmission circuit configured to transmit data to a first node and a second node in response to a first control signal, a latch circuit configured to latch the data received from the data transmission circuit through the first node and the second node, and a data output circuit configured to output the data latched by the latch circuit in response to a second control signal. NMOS transistors contained in the data transmission circuit, the latch circuit, and the data output circuit may be formed in first, fourth, and fifth active regions, PMOS transistors are formed in second and third active regions, and the first to fifth active regions are sequentially arranged in a first direction.