Fuse Latch Redundancy for Reliable Memory Repair
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Solution Overview
Problem
Semiconductor memory devices face challenges in reliably repairing defective memory cells due to the vulnerability of single-bit enable information stored in latch circuits, which can lead to errors during address redirection in repair operations.
Innovation Solution
Implementing a fuse latch circuit with multiple redundant enable latches and an enable logic circuit that determines an overall enable signal based on the states of these latches, reducing the likelihood of information loss and biasing the result towards a default state when most redundant rows are not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single enable latch is used to store enable information, then the device complexity is reduced, but the reliability of enable information storage deteriorates due to vulnerability to latch failures
Solution Approach 1:
The patent applies local quality by making different parts of the enable latch system have different functions: the first enable latch stores the original enable state, while the second enable latch stores a complemented version of the enable state. This functional differentiation within the local latch system improves reliability without significantly increasing overall system complexity.
Solution Approach 2:
The patent implements beforehand cushioning by pre-configuring redundant enable latches with complemented values before any failure occurs. When a latch fails, the complemented value in the redundant latch provides a cushioning effect that allows the system to recover the correct enable state through logical inversion, preventing information loss.
2Reliability
If redundant enable latches are implemented, then the reliability of enable information storage is improved, but the device complexity increases due to additional latch circuits and logic
Solution Approach 1:
The patent segments the enable information storage function into multiple independent enable latches (first enable latch and second enable latch), each storing a portion of the enable state information. This segmentation allows the system to distribute the storage burden and recover from individual latch failures, improving reliability while keeping each segment relatively simple.
Solution Approach 2:
The patent creates a copy of the enable information in the second enable latch, but stores the complemented version rather than an exact copy. This copying approach with inversion reduces the complexity of the recovery logic, as the complemented value can be inverted back to the original state through a simple logical operation when needed.
3Adaptability or versatility
If enable information is stored in latch circuits, then the repair operation functionality is enabled, but the loss of information risk increases due to potential latch failures during address redirection
Solution Approach 1:
The patent implements feedback by continuously monitoring the states of both enable latches and using logic circuits to detect when one latch fails. When a failure is detected, the system provides feedback to switch to the redundant latch, ensuring that enable information is preserved. This feedback mechanism enables the system to adapt to latch failures during repair operations without losing enable information.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses and methods for storing an enable state of an address. The address may be broadcast from a fuse array to a fuse latch, and may be associated with enable information. The fuse latch may include a plurality of enable latch circuits, each of which may receive the enable information in common, and each of which may store the enable information as an enable bit. Each of the enable latch circuits may provide a respective enable signal based on a state of the stored enable bit. An enable logic circuit may provide an overall enable signal with a state determined by the states of all of the enable signals from the plurality of enable latch circuits.