Fuse Latch Testing Circuitry for Memory Redundancy Repair
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Solution Overview
Problem
Memory devices face challenges in accurately testing redundancy latches, particularly those corresponding to unused repair elements, due to functional defects in the memory array, which can impact the reliability of fuse latch functionality and repair processes.
Innovation Solution
Implementing a latch testing circuitry with selection circuitry and a token-based process to individually address and test redundant rows and columns, allowing for more granular testing and reducing the time required for global fuse latch tests by loading known values into fuse latches and comparing them with memory commands, and using OR gates to combine match signals for bank-level status determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional global testing methods are used for fuse latches, then testing coverage can be achieved, but testing time becomes excessively long and granularity is insufficient
Solution Approach 1:
The patent divides the memory array into multiple banks, with each bank containing multiple testing sets of fuse latches. This segmentation allows individual testing sets to be tested independently and in parallel, increasing testing granularity while reducing total testing time through concurrent operations across different banks.
Solution Approach 2:
The patent implements a token-based mechanism that allows selective testing of specific testing sets based on whether repairs are actually needed. Instead of always performing exhaustive global testing, the system can skip testing for banks or testing sets that don't require repair verification, reducing unnecessary testing time while maintaining adequate coverage.
2Reliability
If functional defects in the memory array are present, then array functionality is compromised, but this negatively impacts the accuracy of fuse latch testing
Solution Approach 1:
The patent extracts the fuse latch testing function from the regular memory access path by implementing dedicated testing circuitry and specialized test modes. This separation allows fuse latches to be tested independently of memory array functional defects, ensuring testing accuracy is not compromised by array issues.
Solution Approach 2:
The patent introduces specialized testing circuitry that acts as an intermediary between the memory array and test signals. This intermediary circuitry is designed to be insensitive to array functional defects, allowing accurate fuse latch testing even when the memory array has defects that would normally interfere with testing.
3Reliability
If redundant memory elements are implemented to mitigate failures, then device reliability improves, but device complexity increases
Solution Approach 1:
The patent implements fuse latches that serve multiple functions: they store repair information for redundant elements, can be individually tested through the token-based mechanism, and can be selectively activated based on repair needs. This multi-functionality reduces the need for separate dedicated testing circuits for each latch, thereby reducing overall device complexity while maintaining reliability.
Data Source
AI summary
An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.