Fuse Latch Transistor Merging for Semiconductor Area Reduction
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently arranging peripheral circuits for memory cells, which hinders regional integration and performance in high-speed electronic systems.
Innovation Solution
A fuse latch design incorporating specific configurations of NMOS and PMOS transistors, arranged in active regions to optimize data transmission and latching, allowing for improved regional gain by sharing signal and power lines between adjacent units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional fuse latch designs are used, then the circuit functionality is maintained, but the device width and area increase
Solution Approach 1:
The patent merges multiple transistor functions into shared structures. Specifically, the first and second PMOS transistors share a common source region, and the third and fourth NMOS transistors share a common source region. This merging of components reduces the overall device width while maintaining the latch circuit's functionality.
Solution Approach 2:
The patent rearranges transistor connections to optimize spatial utilization. By configuring the PMOS transistors in parallel between VDD and intermediate nodes, and the NMOS transistors in a complementary arrangement, the design achieves compact width without sacrificing latching capability.
2Reliability
If more transistors are used to ensure reliable latching, then the latching reliability improves, but the device area increases
Solution Approach 1:
The latch circuit uses four transistors (2 PMOS, 2 NMOS) with shared source regions to achieve reliable latching. The first PMOS and second PMOS share a common source connected to VDD, while the third NMOS and fourth NMOS share a common source connected to ground. This merging reduces the peripheral circuit area while maintaining robust latching through the cross-coupled inverter structure.
3Productivity
If fuse-related circuits are arranged traditionally, then the repair functionality is maintained, but the regional gain decreases
Solution Approach 1:
The fuse latch circuit achieves improved regional gain by merging the latching function with compact transistor arrangements. The shared source regions between PMOS and NMOS transistors reduce the area occupied by fuse-related circuits, allowing more efficient packing within the semiconductor device region.
Solution Approach 2:
The latch circuit is segmented into distinct functional blocks: the first inverter formed by the first PMOS and third NMOS, and the second inverter formed by the second PMOS and fourth NMOS. This segmentation allows for systematic arrangement and optimization of fuse-related circuits to improve regional gain.
Data Source
AI summary
A fuse latch of a semiconductor device is disclosed. The fuse latch includes a plurality of PMOS transistors and a plurality of NMOS transistors to latch fuse cell data. In the fuse latch, the PMOS transistors are formed in a single P-type active region, and the NMOS transistors are arranged in a two-stage structure at one side of the P-type active region.