Fuse Logic Selective ECC Decoding for Memory Yield
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining data reliability and accuracy due to defective memory cells, which can lead to incorrect mapping of redundant cells and reduced device yield, especially as production processes mature and fuse component degradation occurs.
Innovation Solution
The implementation of a fuse logic circuitry that selectively enables Error Correction Code (ECC) operations to detect and correct errors in fuse data, allowing for the reuse of fuse arrays for ECC purposes, thereby improving data reliability and reducing the adverse effects of defective cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fuse arrays are designed with large size to compensate for anticipated defective memory cells, then device yield is improved, but portions of the fuse array remain unused as production processes mature
Solution Approach 1:
The fuse array is designed to serve dual purposes: initially for compensating defective memory cells during production, and later for storing error correction code (ECC) data after production processes mature. This multi-functionality ensures that the fuse array remains fully utilized throughout the device lifecycle, eliminating waste while maintaining high device yield.
2Speed
If redundant memory cells are mapped based on inaccurate fuse reads, then mapping speed is maintained, but reliability of memory operation deteriorates
Solution Approach 1:
The system implements ECC (Error Correction Code) mechanisms that provide feedback on fuse read accuracy. When errors are detected in fuse reads, the ECC system generates correction codes that are stored in the fuse array and used to correct the erroneous data, ensuring reliable memory operation while maintaining mapping speed.
Solution Approach 2:
The system performs preliminary ECC encoding and error detection during the fuse read operation itself, before the actual memory mapping occurs. This preliminary action ensures that any errors are identified and corrected in advance, preventing unreliable mapping while maintaining operational speed.
3Device complexity
If fuse component degradation is not addressed, then device complexity remains low, but data accuracy from fuse reads deteriorates
Solution Approach 1:
The ECC system continuously monitors fuse read accuracy and provides feedback through correction codes. As fuse components degrade over time, the ECC mechanism detects increasing error rates and applies appropriate corrections, maintaining data accuracy without requiring complex replacement mechanisms.
Solution Approach 2:
The system changes the operational parameters of the fuse array by repurposing it for ECC data storage alongside its traditional function. This parameter change allows the system to compensate for fuse degradation through software/firmware-based error correction rather than requiring hardware replacement, maintaining accuracy while managing complexity.
Data Source
AI summary
Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.